From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Fri, 10 Mar 2017 02:49:46 +0100 Subject: [U-Boot] [PATCH v2 11/20] arm: socfpga: Add misc support for Arria 10 In-Reply-To: <1489019218-4071-12-git-send-email-ley.foon.tan@intel.com> References: <1489019218-4071-1-git-send-email-ley.foon.tan@intel.com> <1489019218-4071-12-git-send-email-ley.foon.tan@intel.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 03/09/2017 01:26 AM, Ley Foon Tan wrote: > Add misc support for Arria 10 and minor fix on misc Gen5. > > Signed-off-by: Tien Fong Chee > Signed-off-by: Ley Foon Tan > --- > arch/arm/mach-socfpga/Makefile | 1 + > arch/arm/mach-socfpga/include/mach/misc.h | 6 + > arch/arm/mach-socfpga/misc_arria10.c | 254 ++++++++++++++++++++++++++++++ > arch/arm/mach-socfpga/misc_gen5.c | 3 +- > 4 files changed, 263 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/mach-socfpga/misc_arria10.c > > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile > index c494930..9c4617f 100644 > --- a/arch/arm/mach-socfpga/Makefile > +++ b/arch/arm/mach-socfpga/Makefile > @@ -11,6 +11,7 @@ obj-y += misc.o timer.o reset_manager.o clock_manager.o \ > fpga_manager.o board.o > > obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \ > + misc_arria10.o \ > reset_manager_arria10.o > > obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o > diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h > index 64f9b86..446ee0f 100644 > --- a/arch/arm/mach-socfpga/include/mach/misc.h > +++ b/arch/arm/mach-socfpga/include/mach/misc.h > @@ -23,4 +23,10 @@ void socfpga_fpga_add(void); > inline void socfpga_fpga_add(void) {} > #endif > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > +unsigned int dedicated_uart_com_port(const void *blob); > +unsigned int shared_uart_com_port(const void *blob); > +unsigned int uart_com_port(const void *blob); Prefix them with socfpga_ if they're in the global namespace ... > +#endif > + > #endif /* _MISC_H_ */ > diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c > new file mode 100644 > index 0000000..d2bad13 > --- /dev/null > +++ b/arch/arm/mach-socfpga/misc_arria10.c > @@ -0,0 +1,254 @@ > +/* > + * Copyright (C) 2016-2017 Intel Corporation > + * > + * SPDX-License-Identifier: GPL-2.0 > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08 > +#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58 > +#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 0x68 > +#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 0x18 > +#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78 > +#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98 > + > +DECLARE_GLOBAL_DATA_PTR; > + > +static struct pl310_regs *const pl310 = > + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; > +static struct socfpga_system_manager *sysmgr_regs = > + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; > +static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = > + (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; > +static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base = > + (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS; > + > +/* > + * DesignWare Ethernet initialization > + */ > +#ifdef CONFIG_ETH_DESIGNWARE > +void dwmac_deassert_reset(const unsigned int of_reset_id, > + const u32 phymode) > +{ > + u32 reset; > + > + if (of_reset_id == EMAC0_RESET) { > + reset = SOCFPGA_RESET(EMAC0); > + } else if (of_reset_id == EMAC1_RESET) { > + reset = SOCFPGA_RESET(EMAC1); > + } else if (of_reset_id == EMAC2_RESET) { > + reset = SOCFPGA_RESET(EMAC2); > + } else { > + printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); > + return; > + } > + > + clrsetbits_le32(&sysmgr_regs->emac[of_reset_id - EMAC0_RESET], > + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, > + phymode); > + > + /* Release the EMAC controller from reset */ > + socfpga_per_reset(reset, 0); > +} > +#endif > + > +/* > ++ * This function initializes security policies to be consistent across > ++ * all logic units in the Arria 10. > ++ * > ++ * The idea is to set all security policies to be normal, nonsecure > ++ * for all units. > ++ */ > +static void initialize_security_policies(void) > +{ > + /* Put OCRAM in non-secure */ > + writel(0x003f0000, &noc_fw_ocram_base->region0); > + writel(0x1, &noc_fw_ocram_base->enable); > + > + /* Put DDR in non-secure */ > + writel(0xffff0000, &noc_fw_ddr_l3_base->hpsregion0addr); > + writel(0x1, &noc_fw_ddr_l3_base->enable); > +} > + > +int arch_early_init_r(void) > +{ > + initialize_security_policies(); > + > + /* Configure the L2 controller to make SDRAM start at 0 */ > + writel(0x1, &pl310->pl310_addr_filter_start); > + > + /* assert reset to all except L4WD0 and L4TIMER0 */ > + socfpga_per_reset_all(); > + > + /* configuring the clock based on handoff */ > + /* TODO: Add call to cm_basic_init() */ > + > + /* Add device descriptor to FPGA device table */ > + socfpga_fpga_add(); > + return 0; > +} > + > +/* > + * This function looking the 1st encounter UART peripheral, > + * and then return its offset of the dedicated/shared IO pin > + * mux. offset value (zero and above). > + */ > +static int find_peripheral_uart(const void *blob, > + int child, const char *node_name) > +{ > + int len; > + fdt_addr_t base_addr = 0; > + fdt_size_t size; > + const u32 *cell; > + u32 value, offset = 0; > + > + base_addr = fdtdec_get_addr_size(blob, child, "reg", &size); > + if (base_addr != FDT_ADDR_T_NONE) { > + cell = fdt_getprop(blob, child, "pinctrl-single,pins", > + &len); > + if (cell != NULL) { if (!cell) continue; and remove one level of indent ... > + for (; len > 0; len -= (2 * sizeof(u32))) { > + offset = fdt32_to_cpu(*cell++); > + value = fdt32_to_cpu(*cell++); > + /* Found UART peripheral */ > + if (value == 0x0D) > + return offset; > + } > + } > + } > + return -EINVAL; > +} > + > +/* > + * This function looks up the 1st encounter UART peripheral, > + * and then return its offset of the dedicated/shared IO pin > + * mux. UART peripheral is found if the offset is not in negative > + * value. > + */ > +static int is_peripheral_uart_true(const void *blob, > + int node, const char *child_name) > +{ > + int child, len; > + const char *node_name; > + > + child = fdt_first_subnode(blob, node); > + > + if (child < 0) > + return -EINVAL; > + > + node_name = fdt_get_name(blob, child, &len); > + > + while (node_name) { > + if (!strcmp(child_name, node_name)) > + return find_peripheral_uart(blob, child, node_name); > + > + child = fdt_next_subnode(blob, child); > + if (child < 0) > + break; > + > + node_name = fdt_get_name(blob, child, &len); > + } > + > + return -1; > +} > + > +/* > + * This function looking the 1st encounter UART dedicated IO peripheral, > + * and then return based address of the 1st encounter UART dedicated > + * IO peripheral. > + */ > +unsigned int dedicated_uart_com_port(const void *blob) > +{ > + int node; > + > + node = fdtdec_next_compatible(blob, 0, > + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE); > + if (node < 0) > + return 0; > + > + if (is_peripheral_uart_true(blob, node, "dedicated") >= 0) > + return SOCFPGA_UART1_ADDRESS; > + > + return 0; > +} > + > +/* > + * This function looking the 1st encounter UART shared IO peripheral, and then > + * return based address of the 1st encounter UART shared IO peripheral. > + */ > +unsigned int shared_uart_com_port(const void *blob) > +{ > + int node, ret; > + > + node = fdtdec_next_compatible(blob, 0, > + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE); > + if (node < 0) > + return 0; > + > + ret = is_peripheral_uart_true(blob, node, "shared"); > + > + if (ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 || > + ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 || > + ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3) > + return SOCFPGA_UART0_ADDRESS; > + else if (ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 || > + ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 || > + ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3) > + return SOCFPGA_UART1_ADDRESS; > + > + return 0; > +} > + > +/* > + * This function looking the 1st encounter UART peripheral, and then return > + * base address of the 1st encounter UART peripheral. > + */ > +unsigned int uart_com_port(const void *blob) > +{ > + unsigned int ret; > + > + ret = dedicated_uart_com_port(blob); > + > + if (ret) > + return ret; > + > + return shared_uart_com_port(blob); > +} > + > +/* > + * Print CPU information > + */ > +#if defined(CONFIG_DISPLAY_CPUINFO) > +int print_cpuinfo(void) > +{ > + const u32 bsel = (readl(&sysmgr_regs->bootinfo) >> > + SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7; > + > + puts("CPU: Altera SoCFPGA Arria 10\n"); > + > + printf("BOOT: %s\n", bsel_str[bsel].name); > + return 0; > +} > +#endif > + > +#ifdef CONFIG_ARCH_MISC_INIT > +int arch_misc_init(void) > +{ > + return 0; > +} > +#endif > diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c > index f870e1f..3b8ce11 100644 > --- a/arch/arm/mach-socfpga/misc_gen5.c > +++ b/arch/arm/mach-socfpga/misc_gen5.c > @@ -200,7 +200,8 @@ static int socfpga_fpga_id(const bool print_id) > #if defined(CONFIG_DISPLAY_CPUINFO) > int print_cpuinfo(void) > { > - const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; > + const u32 bsel = (readl(&sysmgr_regs->bootinfo) >> > + SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7; > > puts("CPU: Altera SoCFPGA Platform\n"); > socfpga_fpga_id(1); > -- Best regards, Marek Vasut