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Tue, 05 Mar 2024 10:43:20 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 425AhJns001655 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 5 Mar 2024 10:43:19 GMT Received: from [10.214.66.81] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 5 Mar 2024 02:43:15 -0800 Message-ID: Date: Tue, 5 Mar 2024 16:13:12 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH v12 3/9] firmware: qcom: scm: Modify only the download bits in TCSR register Content-Language: en-US To: Bjorn Andersson CC: , , , , , Poovendhan Selvaraj , Kathiravan Thirumoorthy , Dmitry Baryshkov , Elliot Berman References: <20240227155308.18395-1-quic_mojha@quicinc.com> <20240227155308.18395-4-quic_mojha@quicinc.com> From: Mukesh Ojha In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: owAQoPT0hUqYLOay4X0cQRPRi_y6TqrM X-Proofpoint-ORIG-GUID: owAQoPT0hUqYLOay4X0cQRPRi_y6TqrM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-05_08,2024-03-04_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 spamscore=0 adultscore=0 mlxscore=0 phishscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2403050085 On 3/3/2024 12:43 AM, Bjorn Andersson wrote: > On Tue, Feb 27, 2024 at 09:23:02PM +0530, Mukesh Ojha wrote: >> Crashdump collection is done based on DLOAD bits of TCSR register. >> To retain other bits, scm driver need to read the register and >> modify only the DLOAD bits, as other bits in TCSR may have their >> own significance. >> >> Co-developed-by: Poovendhan Selvaraj >> Signed-off-by: Poovendhan Selvaraj >> Signed-off-by: Mukesh Ojha >> Tested-by: Kathiravan Thirumoorthy # IPQ9574 and IPQ5332 >> Reviewed-by: Dmitry Baryshkov >> Reviewed-by: Elliot Berman >> --- >> drivers/firmware/qcom/qcom_scm.c | 14 ++++++++++++-- >> 1 file changed, 12 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c >> index 8f766fce5f7c..bd6bfdf2d828 100644 >> --- a/drivers/firmware/qcom/qcom_scm.c >> +++ b/drivers/firmware/qcom/qcom_scm.c >> @@ -4,6 +4,8 @@ >> */ >> >> #include >> +#include >> +#include >> #include >> #include >> #include >> @@ -114,6 +116,12 @@ static const u8 qcom_scm_cpu_warm_bits[QCOM_SCM_BOOT_MAX_CPUS] = { >> #define QCOM_SMC_WAITQ_FLAG_WAKE_ONE BIT(0) >> #define QCOM_SMC_WAITQ_FLAG_WAKE_ALL BIT(1) >> >> +#define QCOM_DLOAD_MASK GENMASK(5, 4) >> +enum qcom_dload_mode { >> + QCOM_DLOAD_NODUMP = 0, >> + QCOM_DLOAD_FULLDUMP = 1, > > These values are not enumerations, they represent fixed/defined values > in the interface. As such it's appropriate to use #define. > Thanks for giving reasoning on why it should be #define and not enum. -Mukesh