From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from kirsty.vergenet.net ([202.4.237.240]:36101 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752708AbcF3OP7 (ORCPT ); Thu, 30 Jun 2016 10:15:59 -0400 From: Simon Horman To: linux-renesas-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Magnus Damm , Geert Uytterhoeven , Simon Horman Subject: [PATCH 6/9] arm64: dts: r8a7796: Add SYSC PM Domains Date: Thu, 30 Jun 2016 16:15:04 +0200 Message-Id: In-Reply-To: References: Sender: linux-renesas-soc-owner@vger.kernel.org List-ID: From: Geert Uytterhoeven Add a device node for the System Controller. Hook up the Cortex-A57 CPU core and L2 cache/SCU to their respective PM Domains. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 178debf68318..85f0843ddd87 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -10,6 +10,7 @@ #include #include +#include / { compatible = "renesas,r8a7796"; @@ -30,6 +31,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; }; @@ -37,6 +39,7 @@ L2_CA57: cache-controller@0 { compatible = "cache"; reg = <0>; + power-domains = <&sysc R8A7796_PD_CA57_SCU>; cache-unified; cache-level = <2>; }; @@ -104,6 +107,12 @@ #power-domain-cells = <0>; }; + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7796-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + scif2: serial@e6e88000 { compatible = "renesas,scif-r8a7796", "renesas,rcar-gen3-scif", "renesas,scif"; -- 2.7.0.rc3.207.g0ac5344 From mboxrd@z Thu Jan 1 00:00:00 1970 From: horms+renesas@verge.net.au (Simon Horman) Date: Thu, 30 Jun 2016 16:15:04 +0200 Subject: [PATCH 6/9] arm64: dts: r8a7796: Add SYSC PM Domains In-Reply-To: References: Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org From: Geert Uytterhoeven Add a device node for the System Controller. Hook up the Cortex-A57 CPU core and L2 cache/SCU to their respective PM Domains. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 178debf68318..85f0843ddd87 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -10,6 +10,7 @@ #include #include +#include / { compatible = "renesas,r8a7796"; @@ -30,6 +31,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; }; @@ -37,6 +39,7 @@ L2_CA57: cache-controller at 0 { compatible = "cache"; reg = <0>; + power-domains = <&sysc R8A7796_PD_CA57_SCU>; cache-unified; cache-level = <2>; }; @@ -104,6 +107,12 @@ #power-domain-cells = <0>; }; + sysc: system-controller at e6180000 { + compatible = "renesas,r8a7796-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + scif2: serial at e6e88000 { compatible = "renesas,scif-r8a7796", "renesas,rcar-gen3-scif", "renesas,scif"; -- 2.7.0.rc3.207.g0ac5344