* [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions
@ 2021-05-17 20:50 matheus.ferst
2021-05-17 20:50 ` [PATCH v5 01/23] target/ppc: Introduce gen_icount_io_start matheus.ferst
` (23 more replies)
0 siblings, 24 replies; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
This series provides the basic infrastructure for adding the new 32/64-bit
instructions in Power ISA 3.1 to target/ppc.
v5:
- Rebase on ppc-for-6.1;
- Change copyright line from new files;
- Remove argument set from PNOP;
- Add comments to explain helper_cfuged implementation;
- New REQUIRE_ALTIVEC macro;
- REQUIRE_ALTIVEC and REQUIRE_INSNS_FLAGS2 in trans_CFUGED;
- cmp/cmpi/cmpl/cmpli moved to decodetree.
v4:
- Rebase on ppc-for-6.1;
- Fold do_ldst_D and do_ldst_X;
- Add tcg_const_tl, used to share do_ldst_D and do_ldst_X code;
- Unfold prefixed and non-prefixed loads/stores/addi to let non-prefixed insns use the non-prefixed formats;
- PNOP invalid suffixes;
- setbc/setbcr/stnbc/setnbcr implemented;
- cfuged/vcfuged implemented;
- addpcis moved to decodetree.
v3:
- More changes for decodetree.
- Cleanup exception/is_jmp logic to the point exception is removed.
- Fold in Luis' isa check for prefixed insn support.
- Share trans_* between prefixed and non-prefixed instructions.
- Use macros to minimize the trans_* boilerplate.
- Fix decode mistake for STHX/STHXU.
v2:
- Store current pc in ctx instead of insn_size
- Use separate decode files for 32- and 64-bit instructions
- Improvements to the exception/is_jmp logic
- Use translator_loop_temp_check()
- Moved logic to prevent translation from crossing page boundaries
- Additional instructions using decodetree: addis, pnop, loads/stores
- Added check for prefixed insn support in cpu flags
Matheus Ferst (6):
TCG: add tcg_constant_tl
target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions
target/ppc: Implement cfuged instruction
target/ppc: Implement vcfuged instruction
target/ppc: Move addpcis to decodetree
target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree
Richard Henderson (17):
target/ppc: Introduce gen_icount_io_start
target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE
target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN
target/ppc: Remove DisasContext.exception
target/ppc: Move single-step check to ppc_tr_tb_stop
target/ppc: Tidy exception vs exit_tb
target/ppc: Mark helper_raise_exception* as noreturn
target/ppc: Use translator_loop_temp_check
target/ppc: Introduce macros to check isa extensions
target/ppc: Move page crossing check to ppc_tr_translate_insn
target/ppc: Add infrastructure for prefixed insns
target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI
target/ppc: Implement PNOP
target/ppc: Move D/DS/X-form integer loads to decodetree
target/ppc: Implement prefixed integer load instructions
target/ppc: Move D/DS/X-form integer stores to decodetree
target/ppc: Implement prefixed integer store instructions
include/tcg/tcg-op.h | 2 +
linux-user/ppc/cpu_loop.c | 6 -
target/ppc/cpu.h | 4 +-
target/ppc/helper.h | 5 +-
target/ppc/insn32.decode | 126 ++++
target/ppc/insn64.decode | 124 ++++
target/ppc/int_helper.c | 62 ++
target/ppc/meson.build | 9 +
target/ppc/translate.c | 659 +++++----------------
target/ppc/translate/fixedpoint-impl.c.inc | 279 +++++++++
target/ppc/translate/vector-impl.c.inc | 56 ++
11 files changed, 820 insertions(+), 512 deletions(-)
create mode 100644 target/ppc/insn32.decode
create mode 100644 target/ppc/insn64.decode
create mode 100644 target/ppc/translate/fixedpoint-impl.c.inc
create mode 100644 target/ppc/translate/vector-impl.c.inc
--
2.25.1
^ permalink raw reply [flat|nested] 57+ messages in thread
* [PATCH v5 01/23] target/ppc: Introduce gen_icount_io_start
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:13 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 02/23] target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE matheus.ferst
` (22 subsequent siblings)
23 siblings, 1 reply; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Create a function to handle the details for interacting with icount.
Force the exit from the tb via DISAS_TOO_MANY, which allows chaining
to the next tb, where the code emitted for gen_tb_start() will
determine if we must exit. We can thus remove any matching
conditional call to gen_stop_exception.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 174 +++++++++--------------------------------
1 file changed, 39 insertions(+), 135 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index d51a1913a7..060ef83bc0 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -304,6 +304,20 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
ctx->base.is_jmp = DISAS_NORETURN;
}
+static void gen_icount_io_start(DisasContext *ctx)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ /*
+ * An I/O instruction must be last in the TB.
+ * Chain to the next TB, and let the code from gen_tb_start
+ * decide if we need to return to the main loop.
+ * Doing this first also allows this value to be overridden.
+ */
+ ctx->base.is_jmp = DISAS_TOO_MANY;
+ }
+}
+
/*
* Tells the caller what is the appropriate exception to generate and prepares
* SPR registers for this exception.
@@ -540,24 +554,14 @@ void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
#if !defined(CONFIG_USER_ONLY)
void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
#endif
@@ -565,24 +569,14 @@ void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
/* Time base */
void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
@@ -598,24 +592,14 @@ void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
#if !defined(CONFIG_USER_ONLY)
void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
@@ -631,80 +615,45 @@ void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
#if defined(TARGET_PPC64)
void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
/* HDECR */
void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
#endif
@@ -912,71 +861,41 @@ void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
#if !defined(CONFIG_USER_ONLY)
void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_store_spr(sprn, cpu_gpr[gprn]);
gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
/* We must stop translation as we may have rebooted */
gen_stop_exception(ctx);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
#endif
@@ -2860,18 +2779,13 @@ static void gen_darn(DisasContext *ctx)
if (l > 2) {
tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
} else {
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
if (l == 0) {
gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
} else {
/* Return 64-bit random for both CRN and RRN */
gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
}
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
}
#endif
@@ -5013,9 +4927,7 @@ static void gen_rfi(DisasContext *ctx)
}
/* Restore CPU state */
CHK_SV;
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_update_cfar(ctx, ctx->cia);
gen_helper_rfi(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
@@ -5030,9 +4942,7 @@ static void gen_rfid(DisasContext *ctx)
#else
/* Restore CPU state */
CHK_SV;
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_update_cfar(ctx, ctx->cia);
gen_helper_rfid(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
@@ -5047,9 +4957,7 @@ static void gen_rfscv(DisasContext *ctx)
#else
/* Restore CPU state */
CHK_SV;
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_update_cfar(ctx, ctx->cia);
gen_helper_rfscv(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
@@ -5379,9 +5287,7 @@ static void gen_mtmsrd(DisasContext *ctx)
CHK_SV;
#if !defined(CONFIG_USER_ONLY)
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
if (ctx->opcode & 0x00010000) {
/* L=1 form only updates EE and RI */
TCGv t0 = tcg_temp_new();
@@ -5416,9 +5322,7 @@ static void gen_mtmsr(DisasContext *ctx)
CHK_SV;
#if !defined(CONFIG_USER_ONLY)
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
if (ctx->opcode & 0x00010000) {
/* L=1 form only updates EE and RI */
TCGv t0 = tcg_temp_new();
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH v5 02/23] target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
2021-05-17 20:50 ` [PATCH v5 01/23] target/ppc: Introduce gen_icount_io_start matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:14 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 03/23] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN matheus.ferst
` (21 subsequent siblings)
23 siblings, 1 reply; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Remove the synthetic "exception" after no more uses.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
linux-user/ppc/cpu_loop.c | 3 ---
target/ppc/cpu.h | 1 -
target/ppc/translate.c | 24 +++++++-----------------
3 files changed, 7 insertions(+), 21 deletions(-)
diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c
index 4a0f6c8dc2..fe526693d2 100644
--- a/linux-user/ppc/cpu_loop.c
+++ b/linux-user/ppc/cpu_loop.c
@@ -423,9 +423,6 @@ void cpu_loop(CPUPPCState *env)
cpu_abort(cs, "Maintenance exception while in user mode. "
"Aborting\n");
break;
- case POWERPC_EXCP_STOP: /* stop translation */
- /* We did invalidate the instruction cache. Go on */
- break;
case POWERPC_EXCP_BRANCH: /* branch instruction: */
/* We just stopped because of a branch. Go on */
break;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 99ee1e09b2..9e38df685d 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -132,7 +132,6 @@ enum {
/* EOL */
POWERPC_EXCP_NB = 103,
/* QEMU exceptions: used internally during code translation */
- POWERPC_EXCP_STOP = 0x200, /* stop translation */
POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
/* QEMU exceptions: special cases we want to stop translation */
POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 060ef83bc0..f57b67be5f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -369,13 +369,6 @@ static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
}
-/* Stop translation */
-static inline void gen_stop_exception(DisasContext *ctx)
-{
- gen_update_nip(ctx, ctx->base.pc_next);
- ctx->exception = POWERPC_EXCP_STOP;
-}
-
/*****************************************************************************/
/* SPR READ/WRITE CALLBACKS */
@@ -829,7 +822,7 @@ void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
/* Must stop the translation as endianness may have changed */
- gen_stop_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
}
#endif
@@ -877,7 +870,7 @@ void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
gen_store_spr(sprn, cpu_gpr[gprn]);
gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
/* We must stop translation as we may have rebooted */
- gen_stop_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
}
void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
@@ -4080,7 +4073,7 @@ static void gen_isync(DisasContext *ctx)
gen_check_tlb_flush(ctx, false);
}
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
- gen_stop_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
}
#define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
@@ -5312,7 +5305,7 @@ static void gen_mtmsrd(DisasContext *ctx)
gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
}
/* Must stop the translation as machine state (may have) changed */
- gen_stop_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
#endif /* !defined(CONFIG_USER_ONLY) */
}
#endif /* defined(TARGET_PPC64) */
@@ -5355,7 +5348,7 @@ static void gen_mtmsr(DisasContext *ctx)
tcg_temp_free(msr);
}
/* Must stop the translation as machine state (may have) changed */
- gen_stop_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
#endif
}
@@ -7492,7 +7485,7 @@ static void gen_wrtee(DisasContext *ctx)
* Stop translation to have a chance to raise an exception if we
* just set msr_ee to 1
*/
- gen_stop_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -7506,7 +7499,7 @@ static void gen_wrteei(DisasContext *ctx)
if (ctx->opcode & 0x00008000) {
tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
/* Stop translation to have a chance to raise an exception */
- gen_stop_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
} else {
tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
}
@@ -9128,9 +9121,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
case POWERPC_EXCP_BRANCH:
ctx->base.is_jmp = DISAS_NORETURN;
break;
- case POWERPC_EXCP_STOP:
- ctx->base.is_jmp = DISAS_EXIT;
- break;
default:
/* Every other ctx->exception should have set NORETURN. */
g_assert_not_reached();
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH v5 03/23] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
2021-05-17 20:50 ` [PATCH v5 01/23] target/ppc: Introduce gen_icount_io_start matheus.ferst
2021-05-17 20:50 ` [PATCH v5 02/23] target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:15 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 04/23] target/ppc: Remove DisasContext.exception matheus.ferst
` (20 subsequent siblings)
23 siblings, 1 reply; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
The translation of branch instructions always results in exit from
the TB. Remove the synthetic "exception" after no more uses.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
linux-user/ppc/cpu_loop.c | 3 ---
target/ppc/cpu.h | 2 --
target/ppc/translate.c | 8 ++------
3 files changed, 2 insertions(+), 11 deletions(-)
diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c
index fe526693d2..fa91ea0eed 100644
--- a/linux-user/ppc/cpu_loop.c
+++ b/linux-user/ppc/cpu_loop.c
@@ -423,9 +423,6 @@ void cpu_loop(CPUPPCState *env)
cpu_abort(cs, "Maintenance exception while in user mode. "
"Aborting\n");
break;
- case POWERPC_EXCP_BRANCH: /* branch instruction: */
- /* We just stopped because of a branch. Go on */
- break;
case POWERPC_EXCP_SYSCALL_USER:
/* system call in user-mode emulation */
/* WARNING:
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 9e38df685d..cab33a3680 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -131,8 +131,6 @@ enum {
POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception */
/* EOL */
POWERPC_EXCP_NB = 103,
- /* QEMU exceptions: used internally during code translation */
- POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
/* QEMU exceptions: special cases we want to stop translation */
POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
};
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index f57b67be5f..d019454550 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -4692,7 +4692,6 @@ static void gen_b(DisasContext *ctx)
{
target_ulong li, target;
- ctx->exception = POWERPC_EXCP_BRANCH;
/* sign extend LI */
li = LI(ctx->opcode);
li = (li ^ 0x02000000) - 0x02000000;
@@ -4706,6 +4705,7 @@ static void gen_b(DisasContext *ctx)
}
gen_update_cfar(ctx, ctx->cia);
gen_goto_tb(ctx, 0, target);
+ ctx->base.is_jmp = DISAS_NORETURN;
}
#define BCOND_IM 0
@@ -4718,7 +4718,6 @@ static void gen_bcond(DisasContext *ctx, int type)
uint32_t bo = BO(ctx->opcode);
TCGLabel *l1;
TCGv target;
- ctx->exception = POWERPC_EXCP_BRANCH;
if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
target = tcg_temp_local_new();
@@ -4825,6 +4824,7 @@ static void gen_bcond(DisasContext *ctx, int type)
gen_set_label(l1);
gen_goto_tb(ctx, 1, ctx->base.pc_next);
}
+ ctx->base.is_jmp = DISAS_NORETURN;
}
static void gen_bc(DisasContext *ctx)
@@ -9102,7 +9102,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
/* Check trace mode exceptions */
if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
(ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
- ctx->exception != POWERPC_EXCP_BRANCH &&
ctx->base.is_jmp != DISAS_NORETURN)) {
uint32_t excp = gen_prep_dbgex(ctx);
gen_exception_nip(ctx, excp, ctx->base.pc_next);
@@ -9118,9 +9117,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
switch (ctx->exception) {
case POWERPC_EXCP_NONE:
break;
- case POWERPC_EXCP_BRANCH:
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
default:
/* Every other ctx->exception should have set NORETURN. */
g_assert_not_reached();
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH v5 04/23] target/ppc: Remove DisasContext.exception
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
` (2 preceding siblings ...)
2021-05-17 20:50 ` [PATCH v5 03/23] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:17 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 05/23] target/ppc: Move single-step check to ppc_tr_tb_stop matheus.ferst
` (19 subsequent siblings)
23 siblings, 1 reply; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Now that we have removed all of the fake exceptions, and all real
exceptions exit via DISAS_NORETURN, we can remove this field.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 30 ++++--------------------------
1 file changed, 4 insertions(+), 26 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index d019454550..80cd11b3f8 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -159,7 +159,6 @@ struct DisasContext {
DisasContextBase base;
target_ulong cia; /* current instruction address */
uint32_t opcode;
- uint32_t exception;
/* Routine used to access memory */
bool pr, hv, dr, le_mode;
bool lazy_tlb_flush;
@@ -261,15 +260,12 @@ static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
* These are all synchronous exceptions, we set the PC back to the
* faulting instruction
*/
- if (ctx->exception == POWERPC_EXCP_NONE) {
- gen_update_nip(ctx, ctx->cia);
- }
+ gen_update_nip(ctx, ctx->cia);
t0 = tcg_const_i32(excp);
t1 = tcg_const_i32(error);
gen_helper_raise_exception_err(cpu_env, t0, t1);
tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1);
- ctx->exception = excp;
ctx->base.is_jmp = DISAS_NORETURN;
}
@@ -281,13 +277,10 @@ static void gen_exception(DisasContext *ctx, uint32_t excp)
* These are all synchronous exceptions, we set the PC back to the
* faulting instruction
*/
- if (ctx->exception == POWERPC_EXCP_NONE) {
- gen_update_nip(ctx, ctx->cia);
- }
+ gen_update_nip(ctx, ctx->cia);
t0 = tcg_const_i32(excp);
gen_helper_raise_exception(cpu_env, t0);
tcg_temp_free_i32(t0);
- ctx->exception = excp;
ctx->base.is_jmp = DISAS_NORETURN;
}
@@ -300,7 +293,6 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
t0 = tcg_const_i32(excp);
gen_helper_raise_exception(cpu_env, t0);
tcg_temp_free_i32(t0);
- ctx->exception = excp;
ctx->base.is_jmp = DISAS_NORETURN;
}
@@ -4993,13 +4985,10 @@ static void gen_scv(DisasContext *ctx)
uint32_t lev = (ctx->opcode >> 5) & 0x7F;
/* Set the PC back to the faulting instruction. */
- if (ctx->exception == POWERPC_EXCP_NONE) {
- gen_update_nip(ctx, ctx->cia);
- }
+ gen_update_nip(ctx, ctx->cia);
gen_helper_scv(cpu_env, tcg_constant_i32(lev));
- /* This need not be exact, just not POWERPC_EXCP_NONE */
- ctx->exception = POWERPC_SYSCALL_VECTORED;
+ ctx->base.is_jmp = DISAS_NORETURN;
}
#endif
#endif
@@ -9005,7 +8994,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
uint32_t hflags = ctx->base.tb->flags;
int bound;
- ctx->exception = POWERPC_EXCP_NONE;
ctx->spr_cb = env->spr_cb;
ctx->pr = (hflags >> HFLAGS_PR) & 1;
ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7;
@@ -9112,16 +9100,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
"temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode),
opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
}
-
- if (ctx->base.is_jmp == DISAS_NEXT) {
- switch (ctx->exception) {
- case POWERPC_EXCP_NONE:
- break;
- default:
- /* Every other ctx->exception should have set NORETURN. */
- g_assert_not_reached();
- }
- }
}
static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH v5 05/23] target/ppc: Move single-step check to ppc_tr_tb_stop
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
` (3 preceding siblings ...)
2021-05-17 20:50 ` [PATCH v5 04/23] target/ppc: Remove DisasContext.exception matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:19 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 06/23] target/ppc: Tidy exception vs exit_tb matheus.ferst
` (18 subsequent siblings)
23 siblings, 1 reply; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
When single-stepping, force max_insns to 1 in init_disas
so that we exit the translation loop immediately.
Combine the single-step checks in tb_stop, and give the
gdb exception priority over the cpu exception, just as
we already do in gen_lookup_and_goto_ptr.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 33 +++++++++++++++++++--------------
1 file changed, 19 insertions(+), 14 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 80cd11b3f8..05e3c0417a 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -8992,7 +8992,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUPPCState *env = cs->env_ptr;
uint32_t hflags = ctx->base.tb->flags;
- int bound;
ctx->spr_cb = env->spr_cb;
ctx->pr = (hflags >> HFLAGS_PR) & 1;
@@ -9032,8 +9031,12 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
}
- bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
- ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
+ if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP)) {
+ ctx->base.max_insns = 1;
+ } else {
+ int bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
+ ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
+ }
}
static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
@@ -9087,14 +9090,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
handler->count++;
#endif
- /* Check trace mode exceptions */
- if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
- (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
- ctx->base.is_jmp != DISAS_NORETURN)) {
- uint32_t excp = gen_prep_dbgex(ctx);
- gen_exception_nip(ctx, excp, ctx->base.pc_next);
- }
-
if (tcg_check_temp_count()) {
qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked "
"temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode),
@@ -9107,6 +9102,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
DisasContext *ctx = container_of(dcbase, DisasContext, base);
DisasJumpType is_jmp = ctx->base.is_jmp;
target_ulong nip = ctx->base.pc_next;
+ int sse;
if (is_jmp == DISAS_NORETURN) {
/* We have already exited the TB. */
@@ -9114,7 +9110,8 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
}
/* Honor single stepping. */
- if (unlikely(ctx->base.singlestep_enabled)) {
+ sse = ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP);
+ if (unlikely(sse)) {
switch (is_jmp) {
case DISAS_TOO_MANY:
case DISAS_EXIT_UPDATE:
@@ -9127,8 +9124,16 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
default:
g_assert_not_reached();
}
- gen_debug_exception(ctx);
- return;
+
+ if (sse & GDBSTUB_SINGLE_STEP) {
+ gen_debug_exception(ctx);
+ return;
+ }
+ /* else CPU_SINGLE_STEP... */
+ if (nip <= 0x100 || nip > 0xf00) {
+ gen_exception(ctx, gen_prep_dbgex(ctx));
+ return;
+ }
}
switch (is_jmp) {
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH v5 06/23] target/ppc: Tidy exception vs exit_tb
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
` (4 preceding siblings ...)
2021-05-17 20:50 ` [PATCH v5 05/23] target/ppc: Move single-step check to ppc_tr_tb_stop matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:19 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 07/23] target/ppc: Mark helper_raise_exception* as noreturn matheus.ferst
` (17 subsequent siblings)
23 siblings, 1 reply; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
We do not need to emit an exit_tb after an exception,
as the latter will exit via longjmp.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 05e3c0417a..e68152810e 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -4648,8 +4648,9 @@ static void gen_lookup_and_goto_ptr(DisasContext *ctx)
} else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) {
uint32_t excp = gen_prep_dbgex(ctx);
gen_exception(ctx, excp);
+ } else {
+ tcg_gen_exit_tb(NULL, 0);
}
- tcg_gen_exit_tb(NULL, 0);
} else {
tcg_gen_lookup_and_goto_ptr();
}
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH v5 07/23] target/ppc: Mark helper_raise_exception* as noreturn
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
` (5 preceding siblings ...)
2021-05-17 20:50 ` [PATCH v5 06/23] target/ppc: Tidy exception vs exit_tb matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:20 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 08/23] target/ppc: Use translator_loop_temp_check matheus.ferst
` (16 subsequent siblings)
23 siblings, 1 reply; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/helper.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 513066d54d..ea9f2a236c 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -1,5 +1,5 @@
-DEF_HELPER_FLAGS_3(raise_exception_err, TCG_CALL_NO_WG, void, env, i32, i32)
-DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, void, env, i32)
+DEF_HELPER_FLAGS_3(raise_exception_err, TCG_CALL_NO_WG, noreturn, env, i32, i32)
+DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32)
DEF_HELPER_FLAGS_4(tw, TCG_CALL_NO_WG, void, env, tl, tl, i32)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_4(td, TCG_CALL_NO_WG, void, env, tl, tl, i32)
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH v5 08/23] target/ppc: Use translator_loop_temp_check
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
` (6 preceding siblings ...)
2021-05-17 20:50 ` [PATCH v5 07/23] target/ppc: Mark helper_raise_exception* as noreturn matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:20 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 09/23] target/ppc: Introduce macros to check isa extensions matheus.ferst
` (15 subsequent siblings)
23 siblings, 1 reply; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
The special logging is unnecessary. It will have been done
immediately before in the log file.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
---
target/ppc/translate.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index e68152810e..ea200f9637 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -9091,11 +9091,7 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
handler->count++;
#endif
- if (tcg_check_temp_count()) {
- qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked "
- "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode),
- opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
- }
+ translator_loop_temp_check(&ctx->base);
}
static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH v5 09/23] target/ppc: Introduce macros to check isa extensions
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
` (7 preceding siblings ...)
2021-05-17 20:50 ` [PATCH v5 08/23] target/ppc: Use translator_loop_temp_check matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:21 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 10/23] target/ppc: Move page crossing check to ppc_tr_translate_insn matheus.ferst
` (14 subsequent siblings)
23 siblings, 1 reply; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
These will be used by the decodetree trans_* functions
to early-exit when the instruction set is not enabled.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index ea200f9637..dc0f5fafc2 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7750,6 +7750,32 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high)
tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
}
+/*
+ * Helpers for trans_* functions to check for specific insns flags.
+ * Use token pasting to ensure that we use the proper flag with the
+ * proper variable.
+ */
+#define REQUIRE_INSNS_FLAGS(CTX, NAME) \
+ do { \
+ if (((CTX)->insns_flags & PPC_##NAME) == 0) { \
+ return false; \
+ } \
+ } while (0)
+
+#define REQUIRE_INSNS_FLAGS2(CTX, NAME) \
+ do { \
+ if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \
+ return false; \
+ } \
+ } while (0)
+
+/* Then special-case the check for 64-bit so that we elide code for ppc32. */
+#if TARGET_LONG_BITS == 32
+# define REQUIRE_64BIT(CTX) return false
+#else
+# define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B)
+#endif
+
#include "translate/fp-impl.c.inc"
#include "translate/vmx-impl.c.inc"
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH v5 10/23] target/ppc: Move page crossing check to ppc_tr_translate_insn
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
` (8 preceding siblings ...)
2021-05-17 20:50 ` [PATCH v5 09/23] target/ppc: Introduce macros to check isa extensions matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:23 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 11/23] target/ppc: Add infrastructure for prefixed insns matheus.ferst
` (13 subsequent siblings)
23 siblings, 1 reply; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
With prefixed instructions, the number of instructions
remaining until the page crossing is no longer constant.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index dc0f5fafc2..b1873d2dcc 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -9060,9 +9060,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP)) {
ctx->base.max_insns = 1;
- } else {
- int bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
- ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
}
}
@@ -9117,6 +9114,11 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
handler->count++;
#endif
+ /* End the TB when crossing a page boundary. */
+ if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) {
+ ctx->base.is_jmp = DISAS_TOO_MANY;
+ }
+
translator_loop_temp_check(&ctx->base);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH v5 11/23] target/ppc: Add infrastructure for prefixed insns
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
` (9 preceding siblings ...)
2021-05-17 20:50 ` [PATCH v5 10/23] target/ppc: Move page crossing check to ppc_tr_translate_insn matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:25 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 12/23] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI matheus.ferst
` (12 subsequent siblings)
23 siblings, 1 reply; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/cpu.h | 1 +
target/ppc/insn32.decode | 18 ++++++++++++
target/ppc/insn64.decode | 18 ++++++++++++
target/ppc/meson.build | 9 ++++++
target/ppc/translate.c | 34 +++++++++++++++++++---
target/ppc/translate/fixedpoint-impl.c.inc | 18 ++++++++++++
6 files changed, 94 insertions(+), 4 deletions(-)
create mode 100644 target/ppc/insn32.decode
create mode 100644 target/ppc/insn64.decode
create mode 100644 target/ppc/translate/fixedpoint-impl.c.inc
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index cab33a3680..351fcdf5f8 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -144,6 +144,7 @@ enum {
POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
+ POWERPC_EXCP_ALIGN_INSN = 0x07, /* Pref. insn x-ing 64-byte boundary */
/* Exception subtypes for POWERPC_EXCP_PROGRAM */
/* FP exceptions */
POWERPC_EXCP_FP = 0x10,
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
new file mode 100644
index 0000000000..a3a8ae06bf
--- /dev/null
+++ b/target/ppc/insn32.decode
@@ -0,0 +1,18 @@
+#
+# Power ISA decode for 32-bit insns (opcode space 0)
+#
+# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+#
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
new file mode 100644
index 0000000000..a38b1f84dc
--- /dev/null
+++ b/target/ppc/insn64.decode
@@ -0,0 +1,18 @@
+#
+# Power ISA decode for 64-bit prefixed insns (opcode space 0 and 1)
+#
+# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+#
diff --git a/target/ppc/meson.build b/target/ppc/meson.build
index d1aa7d5d39..512e3a0288 100644
--- a/target/ppc/meson.build
+++ b/target/ppc/meson.build
@@ -17,6 +17,15 @@ ppc_ss.add(files(
ppc_ss.add(libdecnumber)
+gen = [
+ decodetree.process('insn32.decode',
+ extra_args: '--static-decode=decode_insn32'),
+ decodetree.process('insn64.decode',
+ extra_args: ['--static-decode=decode_insn64',
+ '--insnwidth=64']),
+]
+ppc_ss.add(gen)
+
ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c'))
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b1873d2dcc..64d6acb078 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7776,6 +7776,10 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high)
# define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B)
#endif
+#include "decode-insn32.c.inc"
+#include "decode-insn64.c.inc"
+#include "translate/fixedpoint-impl.c.inc"
+
#include "translate/fp-impl.c.inc"
#include "translate/vmx-impl.c.inc"
@@ -9089,11 +9093,18 @@ static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
return true;
}
+static bool is_prefix_insn(DisasContext *ctx, uint32_t insn)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ return opc1(insn) == 1;
+}
+
static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = cs->env_ptr;
+ target_ulong pc;
uint32_t insn;
bool ok;
@@ -9101,11 +9112,26 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
- ctx->cia = ctx->base.pc_next;
- insn = translator_ldl_swap(env, ctx->base.pc_next, need_byteswap(ctx));
- ctx->base.pc_next += 4;
+ ctx->cia = pc = ctx->base.pc_next;
+ insn = translator_ldl_swap(env, pc, need_byteswap(ctx));
+ ctx->base.pc_next = pc += 4;
- ok = decode_legacy(cpu, ctx, insn);
+ if (!is_prefix_insn(ctx, insn)) {
+ ok = (decode_insn32(ctx, insn) ||
+ decode_legacy(cpu, ctx, insn));
+ } else if ((pc & 63) == 0) {
+ /*
+ * Power v3.1, section 1.9 Exceptions:
+ * attempt to execute a prefixed instruction that crosses a
+ * 64-byte address boundary (system alignment error).
+ */
+ gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN);
+ ok = true;
+ } else {
+ uint32_t insn2 = translator_ldl_swap(env, pc, need_byteswap(ctx));
+ ctx->base.pc_next = pc += 4;
+ ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn));
+ }
if (!ok) {
gen_invalid(ctx);
}
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
new file mode 100644
index 0000000000..be75085cee
--- /dev/null
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -0,0 +1,18 @@
+/*
+ * Power ISA decode for Fixed-Point Facility instructions
+ *
+ * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH v5 12/23] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
` (10 preceding siblings ...)
2021-05-17 20:50 ` [PATCH v5 11/23] target/ppc: Add infrastructure for prefixed insns matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:35 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 13/23] target/ppc: Implement PNOP matheus.ferst
` (11 subsequent siblings)
23 siblings, 1 reply; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 8 ++++
target/ppc/insn64.decode | 12 ++++++
target/ppc/translate.c | 29 --------------
target/ppc/translate/fixedpoint-impl.c.inc | 44 ++++++++++++++++++++++
4 files changed, 64 insertions(+), 29 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index a3a8ae06bf..e7c062d8b4 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -16,3 +16,11 @@
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
+
+&D rt ra si:int64_t
+@D ...... rt:5 ra:5 si:s16 &D
+
+### Fixed-Point Arithmetic Instructions
+
+ADDI 001110 ..... ..... ................ @D
+ADDIS 001111 ..... ..... ................ @D
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index a38b1f84dc..1965088915 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -16,3 +16,15 @@
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
+
+# Format MLS:D and 8LS:D
+&PLS_D rt ra si:int64_t r:bool
+%pls_si 32:s18 0:16
+@PLS_D ...... .. ... r:1 .. .................. \
+ ...... rt:5 ra:5 ................ \
+ &PLS_D si=%pls_si
+
+### Fixed-Point Arithmetic Instructions
+
+PADDI 000001 10 0--.-- .................. \
+ 001110 ..... ..... ................ @PLS_D
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 64d6acb078..5bf9001141 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1846,19 +1846,6 @@ GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0);
/* addze addze. addzeo addzeo.*/
GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0)
GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
-/* addi */
-static void gen_addi(DisasContext *ctx)
-{
- target_long simm = SIMM(ctx->opcode);
-
- if (rA(ctx->opcode) == 0) {
- /* li case */
- tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
- } else {
- tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
- cpu_gpr[rA(ctx->opcode)], simm);
- }
-}
/* addic addic.*/
static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
{
@@ -1878,20 +1865,6 @@ static void gen_addic_(DisasContext *ctx)
gen_op_addic(ctx, 1);
}
-/* addis */
-static void gen_addis(DisasContext *ctx)
-{
- target_long simm = SIMM(ctx->opcode);
-
- if (rA(ctx->opcode) == 0) {
- /* lis case */
- tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
- } else {
- tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
- cpu_gpr[rA(ctx->opcode)], simm << 16);
- }
-}
-
/* addpcis */
static void gen_addpcis(DisasContext *ctx)
{
@@ -7903,10 +7876,8 @@ GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
-GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
-GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index be75085cee..344a3ed54b 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -16,3 +16,47 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+
+/*
+ * Incorporate CIA into the constant when R=1.
+ * Validate that when R=1, RA=0.
+ */
+static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
+{
+ d->rt = a->rt;
+ d->ra = a->ra;
+ d->si = a->si;
+ if (a->r) {
+ if (unlikely(a->ra != 0)) {
+ gen_invalid(ctx);
+ return false;
+ }
+ d->si += ctx->cia;
+ }
+ return true;
+}
+
+static bool trans_ADDI(DisasContext *ctx, arg_D *a)
+{
+ if (a->ra) {
+ tcg_gen_addi_tl(cpu_gpr[a->rt], cpu_gpr[a->ra], a->si);
+ } else {
+ tcg_gen_movi_tl(cpu_gpr[a->rt], a->si);
+ }
+ return true;
+}
+
+static bool trans_PADDI(DisasContext *ctx, arg_PLS_D *a)
+{
+ arg_D d;
+ if (!resolve_PLS_D(ctx, &d, a)) {
+ return true;
+ }
+ return trans_ADDI(ctx, &d);
+}
+
+static bool trans_ADDIS(DisasContext *ctx, arg_D *a)
+{
+ a->si <<= 16;
+ return trans_ADDI(ctx, a);
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH v5 13/23] target/ppc: Implement PNOP
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
` (11 preceding siblings ...)
2021-05-17 20:50 ` [PATCH v5 12/23] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:36 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 14/23] TCG: add tcg_constant_tl matheus.ferst
` (10 subsequent siblings)
23 siblings, 1 reply; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
The illegal suffix behavior matches what was observed in a
POWER10 DD2.0 machine.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v5:
- Remove argument set from PNOP;
- Use no_overlap_group for invalid suffixes.
---
target/ppc/insn64.decode | 67 ++++++++++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 11 ++++
2 files changed, 78 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 1965088915..9aa5097a98 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -28,3 +28,70 @@
PADDI 000001 10 0--.-- .................. \
001110 ..... ..... ................ @PLS_D
+
+### Prefixed No-operation Instruction
+
+@PNOP 000001 11 0000-- 000000000000000000 \
+ ................................
+
+{
+ [
+ ## Invalid suffixes: Branch instruction
+ # bc[l][a]
+ INVALID ................................ \
+ 010000-------------------------- @PNOP
+ # b[l][a]
+ INVALID ................................ \
+ 010010-------------------------- @PNOP
+ # bclr[l]
+ INVALID ................................ \
+ 010011---------------0000010000- @PNOP
+ # bcctr[l]
+ INVALID ................................ \
+ 010011---------------1000010000- @PNOP
+ # bctar[l]
+ INVALID ................................ \
+ 010011---------------1000110000- @PNOP
+
+ ## Invalid suffixes: rfebb
+ INVALID ................................ \
+ 010011---------------0010010010- @PNOP
+
+ ## Invalid suffixes: context synchronizing other than isync
+ # sc
+ INVALID ................................ \
+ 010001------------------------1- @PNOP
+ # scv
+ INVALID ................................ \
+ 010001------------------------01 @PNOP
+ # rfscv
+ INVALID ................................ \
+ 010011---------------0001010010- @PNOP
+ # rfid
+ INVALID ................................ \
+ 010011---------------0000010010- @PNOP
+ # hrfid
+ INVALID ................................ \
+ 010011---------------0100010010- @PNOP
+ # urfid
+ INVALID ................................ \
+ 010011---------------0100110010- @PNOP
+ # stop
+ INVALID ................................ \
+ 010011---------------0101110010- @PNOP
+ # mtmsr w/ L=0
+ INVALID ................................ \
+ 011111---------0-----0010010010- @PNOP
+ # mtmsrd w/ L=0
+ INVALID ................................ \
+ 011111---------0-----0010110010- @PNOP
+
+ ## Invalid suffixes: Service Processor Attention
+ INVALID ................................ \
+ 000000----------------100000000- @PNOP
+ ]
+
+ ## Valid suffixes
+ PNOP ................................ \
+ -------------------------------- @PNOP
+}
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 344a3ed54b..ce034a14a7 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -60,3 +60,14 @@ static bool trans_ADDIS(DisasContext *ctx, arg_D *a)
a->si <<= 16;
return trans_ADDI(ctx, a);
}
+
+static bool trans_INVALID(DisasContext *ctx, arg_INVALID *a)
+{
+ gen_invalid(ctx);
+ return true;
+}
+
+static bool trans_PNOP(DisasContext *ctx, arg_PNOP *a)
+{
+ return true;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH v5 14/23] TCG: add tcg_constant_tl
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
` (12 preceding siblings ...)
2021-05-17 20:50 ` [PATCH v5 13/23] target/ppc: Implement PNOP matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:37 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 15/23] target/ppc: Move D/DS/X-form integer loads to decodetree matheus.ferst
` (9 subsequent siblings)
23 siblings, 1 reply; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Used in D/DS/X-form load/store implementation.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
include/tcg/tcg-op.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index 2cd1faf9c4..ef8a008ea7 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -1096,6 +1096,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
#define tcg_gen_sextract_tl tcg_gen_sextract_i64
#define tcg_gen_extract2_tl tcg_gen_extract2_i64
#define tcg_const_tl tcg_const_i64
+#define tcg_constant_tl tcg_constant_i64
#define tcg_const_local_tl tcg_const_local_i64
#define tcg_gen_movcond_tl tcg_gen_movcond_i64
#define tcg_gen_add2_tl tcg_gen_add2_i64
@@ -1209,6 +1210,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
#define tcg_gen_sextract_tl tcg_gen_sextract_i32
#define tcg_gen_extract2_tl tcg_gen_extract2_i32
#define tcg_const_tl tcg_const_i32
+#define tcg_constant_tl tcg_constant_i32
#define tcg_const_local_tl tcg_const_local_i32
#define tcg_gen_movcond_tl tcg_gen_movcond_i32
#define tcg_gen_add2_tl tcg_gen_add2_i32
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH v5 15/23] target/ppc: Move D/DS/X-form integer loads to decodetree
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
` (13 preceding siblings ...)
2021-05-17 20:50 ` [PATCH v5 14/23] TCG: add tcg_constant_tl matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:44 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 16/23] target/ppc: Implement prefixed integer load instructions matheus.ferst
` (8 subsequent siblings)
23 siblings, 1 reply; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
These are all connected by macros in the legacy decoding.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 37 ++++++
target/ppc/translate.c | 147 ++++-----------------
target/ppc/translate/fixedpoint-impl.c.inc | 89 +++++++++++++
3 files changed, 150 insertions(+), 123 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index e7c062d8b4..70f64c235b 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -20,6 +20,43 @@
&D rt ra si:int64_t
@D ...... rt:5 ra:5 si:s16 &D
+%ds_si 2:s14 !function=times_4
+@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
+
+&X rt ra rb
+@X ...... rt:5 ra:5 rb:5 .......... . &X
+
+### Fixed-Point Load Instructions
+
+LBZ 100010 ..... ..... ................ @D
+LBZU 100011 ..... ..... ................ @D
+LBZX 011111 ..... ..... ..... 0001010111 - @X
+LBZUX 011111 ..... ..... ..... 0001110111 - @X
+
+LHZ 101000 ..... ..... ................ @D
+LHZU 101001 ..... ..... ................ @D
+LHZX 011111 ..... ..... ..... 0100010111 - @X
+LHZUX 011111 ..... ..... ..... 0100110111 - @X
+
+LHA 101010 ..... ..... ................ @D
+LHAU 101011 ..... ..... ................ @D
+LHAX 011111 ..... ..... ..... 0101010111 - @X
+LHAXU 011111 ..... ..... ..... 0101110111 - @X
+
+LWZ 100000 ..... ..... ................ @D
+LWZU 100001 ..... ..... ................ @D
+LWZX 011111 ..... ..... ..... 0000010111 - @X
+LWZUX 011111 ..... ..... ..... 0000110111 - @X
+
+LWA 111010 ..... ..... ..............10 @DS
+LWAX 011111 ..... ..... ..... 0101010101 - @X
+LWAUX 011111 ..... ..... ..... 0101110101 - @X
+
+LD 111010 ..... ..... ..............00 @DS
+LDU 111010 ..... ..... ..............01 @DS
+LDX 011111 ..... ..... ..... 0000010101 - @X
+LDUX 011111 ..... ..... ..... 0000110101 - @X
+
### Fixed-Point Arithmetic Instructions
ADDI 001110 ..... ..... ................ @D
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 5bf9001141..e037efcfe1 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3409,54 +3409,6 @@ GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
#endif
-#define GEN_LD(name, ldop, opc, type) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_imm_index(ctx, EA, 0); \
- gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
-}
-
-#define GEN_LDU(name, ldop, opc, type) \
-static void glue(gen_, name##u)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- if (unlikely(rA(ctx->opcode) == 0 || \
- rA(ctx->opcode) == rD(ctx->opcode))) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- if (type == PPC_64B) \
- gen_addr_imm_index(ctx, EA, 0x03); \
- else \
- gen_addr_imm_index(ctx, EA, 0); \
- gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
-}
-
-#define GEN_LDUX(name, ldop, opc2, opc3, type) \
-static void glue(gen_, name##ux)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- if (unlikely(rA(ctx->opcode) == 0 || \
- rA(ctx->opcode) == rD(ctx->opcode))) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_reg_index(ctx, EA); \
- gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
-}
-
#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
static void glue(gen_, name##x)(DisasContext *ctx) \
{ \
@@ -3475,21 +3427,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) \
#define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
-#define GEN_LDS(name, ldop, op, type) \
-GEN_LD(name, ldop, op | 0x20, type); \
-GEN_LDU(name, ldop, op | 0x21, type); \
-GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
-GEN_LDX(name, ldop, 0x17, op | 0x00, type)
-
-/* lbz lbzu lbzux lbzx */
-GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
-/* lha lhau lhaux lhax */
-GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
-/* lhz lhzu lhzux lhzx */
-GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
-/* lwz lwzu lwzux lwzx */
-GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
-
#define GEN_LDEPX(name, ldop, opc2, opc3) \
static void glue(gen_, name##epx)(DisasContext *ctx) \
{ \
@@ -3510,47 +3447,12 @@ GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
#endif
#if defined(TARGET_PPC64)
-/* lwaux */
-GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
-/* lwax */
-GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
-/* ldux */
-GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
-/* ldx */
-GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
-
/* CI load/store variants */
GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
-static void gen_ld(DisasContext *ctx)
-{
- TCGv EA;
- if (Rc(ctx->opcode)) {
- if (unlikely(rA(ctx->opcode) == 0 ||
- rA(ctx->opcode) == rD(ctx->opcode))) {
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
- return;
- }
- }
- gen_set_access_type(ctx, ACCESS_INT);
- EA = tcg_temp_new();
- gen_addr_imm_index(ctx, EA, 0x03);
- if (ctx->opcode & 0x02) {
- /* lwa (lwau is undefined) */
- gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
- } else {
- /* ld - ldu */
- gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
- }
- if (Rc(ctx->opcode)) {
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
- }
- tcg_temp_free(EA);
-}
-
/* lq */
static void gen_lq(DisasContext *ctx)
{
@@ -7723,6 +7625,14 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high)
tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
}
+/*
+ * Helpers for decodetree used by !function for decoding arguments.
+ */
+static int times_4(DisasContext *ctx, int x)
+{
+ return x * 4;
+}
+
/*
* Helpers for trans_* functions to check for specific insns flags.
* Use token pasting to ensure that we use the proper flag with the
@@ -7749,6 +7659,21 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high)
# define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B)
#endif
+/*
+ * Helpers for implementing sets of trans_* functions.
+ * Defer the implementation of NAME to FUNC, with optional extra arguments.
+ */
+#define TRANS(NAME, FUNC, ...) \
+ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+ { return FUNC(ctx, a, __VA_ARGS__); }
+
+#define TRANS64(NAME, FUNC, ...) \
+ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+ { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); }
+
+/* TODO: More TRANS* helpers for extra insn_flags checks. */
+
+
#include "decode-insn32.c.inc"
#include "decode-insn64.c.inc"
#include "translate/fixedpoint-impl.c.inc"
@@ -7933,7 +7858,6 @@ GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
PPC_NONE, PPC2_ISA300),
#endif
#if defined(TARGET_PPC64)
-GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
#endif
@@ -8299,34 +8223,11 @@ GEN_PPC64_R2(rldcr, 0x1E, 0x09),
GEN_PPC64_R4(rldimi, 0x1E, 0x06),
#endif
-#undef GEN_LD
-#undef GEN_LDU
-#undef GEN_LDUX
#undef GEN_LDX_E
-#undef GEN_LDS
-#define GEN_LD(name, ldop, opc, type) \
-GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_LDU(name, ldop, opc, type) \
-GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_LDUX(name, ldop, opc2, opc3, type) \
-GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
-#define GEN_LDS(name, ldop, op, type) \
-GEN_LD(name, ldop, op | 0x20, type) \
-GEN_LDU(name, ldop, op | 0x21, type) \
-GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
-GEN_LDX(name, ldop, 0x17, op | 0x00, type)
-
-GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
-GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
-GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
-GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
+
#if defined(TARGET_PPC64)
-GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
-GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
-GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
-GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
/* HV/P7 and later only */
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index ce034a14a7..6140dd41ca 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -36,6 +36,95 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
return true;
}
+/*
+ * Fixed-Point Load/Store Instructions
+ */
+
+static bool do_ldst(DisasContext *ctx, int rt, int ra, TCGv displ, bool update,
+ bool store, MemOp mop)
+{
+ TCGv ea;
+
+ if (update && (ra == 0 || (!store && ra == rt))) {
+ gen_invalid(ctx);
+ return true;
+ }
+ gen_set_access_type(ctx, ACCESS_INT);
+
+ ea = tcg_temp_new();
+ if (ra) {
+ tcg_gen_add_tl(ea, cpu_gpr[ra], displ);
+ } else {
+ tcg_gen_mov_tl(ea, displ);
+ }
+ if (NARROW_MODE(ctx)) {
+ tcg_gen_ext32u_tl(ea, ea);
+ }
+ mop ^= ctx->default_tcg_memop_mask;
+ if (store) {
+ tcg_gen_qemu_st_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
+ } else {
+ tcg_gen_qemu_ld_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
+ }
+ if (update) {
+ tcg_gen_mov_tl(cpu_gpr[ra], ea);
+ }
+ tcg_temp_free(ea);
+
+ return true;
+}
+
+static bool do_ldst_D(DisasContext *ctx, arg_D *a, bool update, bool store,
+ MemOp mop)
+{
+ return do_ldst(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store, mop);
+}
+
+static bool do_ldst_X(DisasContext *ctx, arg_X *a, bool update,
+ bool store, MemOp mop)
+{
+ return do_ldst(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, mop);
+}
+
+/* Load Byte and Zero */
+TRANS(LBZ, do_ldst_D, false, false, MO_UB)
+TRANS(LBZX, do_ldst_X, false, false, MO_UB)
+TRANS(LBZU, do_ldst_D, true, false, MO_UB)
+TRANS(LBZUX, do_ldst_X, true, false, MO_UB)
+
+/* Load Halfword and Zero */
+TRANS(LHZ, do_ldst_D, false, false, MO_UW)
+TRANS(LHZX, do_ldst_X, false, false, MO_UW)
+TRANS(LHZU, do_ldst_D, true, false, MO_UW)
+TRANS(LHZUX, do_ldst_X, true, false, MO_UW)
+
+/* Load Halfword Algebraic */
+TRANS(LHA, do_ldst_D, false, false, MO_SW)
+TRANS(LHAX, do_ldst_X, false, false, MO_SW)
+TRANS(LHAU, do_ldst_D, true, false, MO_SW)
+TRANS(LHAXU, do_ldst_X, true, false, MO_SW)
+
+/* Load Word and Zero */
+TRANS(LWZ, do_ldst_D, false, false, MO_UL)
+TRANS(LWZX, do_ldst_X, false, false, MO_UL)
+TRANS(LWZU, do_ldst_D, true, false, MO_UL)
+TRANS(LWZUX, do_ldst_X, true, false, MO_UL)
+
+/* Load Word Algebraic */
+TRANS64(LWA, do_ldst_D, false, false, MO_SL)
+TRANS64(LWAX, do_ldst_X, false, false, MO_SL)
+TRANS64(LWAUX, do_ldst_X, true, false, MO_SL)
+
+/* Load Doubleword */
+TRANS64(LD, do_ldst_D, false, false, MO_Q)
+TRANS64(LDX, do_ldst_X, false, false, MO_Q)
+TRANS64(LDU, do_ldst_D, true, false, MO_Q)
+TRANS64(LDUX, do_ldst_X, true, false, MO_Q)
+
+/*
+ * Fixed-Point Arithmetic Instructions
+ */
+
static bool trans_ADDI(DisasContext *ctx, arg_D *a)
{
if (a->ra) {
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH v5 16/23] target/ppc: Implement prefixed integer load instructions
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
` (14 preceding siblings ...)
2021-05-17 20:50 ` [PATCH v5 15/23] target/ppc: Move D/DS/X-form integer loads to decodetree matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:45 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 17/23] target/ppc: Move D/DS/X-form integer stores to decodetree matheus.ferst
` (7 subsequent siblings)
23 siblings, 1 reply; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn64.decode | 15 +++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 16 ++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 9aa5097a98..547bd1736f 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -24,6 +24,21 @@
...... rt:5 ra:5 ................ \
&PLS_D si=%pls_si
+### Fixed-Point Load Instructions
+
+PLBZ 000001 10 0--.-- .................. \
+ 100010 ..... ..... ................ @PLS_D
+PLHZ 000001 10 0--.-- .................. \
+ 101000 ..... ..... ................ @PLS_D
+PLHA 000001 10 0--.-- .................. \
+ 101010 ..... ..... ................ @PLS_D
+PLWZ 000001 10 0--.-- .................. \
+ 100000 ..... ..... ................ @PLS_D
+PLWA 000001 00 0--.-- .................. \
+ 101001 ..... ..... ................ @PLS_D
+PLD 000001 00 0--.-- .................. \
+ 111001 ..... ..... ................ @PLS_D
+
### Fixed-Point Arithmetic Instructions
PADDI 000001 10 0--.-- .................. \
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 6140dd41ca..7687f31d6f 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -80,6 +80,16 @@ static bool do_ldst_D(DisasContext *ctx, arg_D *a, bool update, bool store,
return do_ldst(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store, mop);
}
+static bool do_ldst_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool update,
+ bool store, MemOp mop)
+{
+ arg_D d;
+ if (!resolve_PLS_D(ctx, &d, a)) {
+ return true;
+ }
+ return do_ldst_D(ctx, &d, update, store, mop);
+}
+
static bool do_ldst_X(DisasContext *ctx, arg_X *a, bool update,
bool store, MemOp mop)
{
@@ -91,35 +101,41 @@ TRANS(LBZ, do_ldst_D, false, false, MO_UB)
TRANS(LBZX, do_ldst_X, false, false, MO_UB)
TRANS(LBZU, do_ldst_D, true, false, MO_UB)
TRANS(LBZUX, do_ldst_X, true, false, MO_UB)
+TRANS(PLBZ, do_ldst_PLS_D, false, false, MO_UB)
/* Load Halfword and Zero */
TRANS(LHZ, do_ldst_D, false, false, MO_UW)
TRANS(LHZX, do_ldst_X, false, false, MO_UW)
TRANS(LHZU, do_ldst_D, true, false, MO_UW)
TRANS(LHZUX, do_ldst_X, true, false, MO_UW)
+TRANS(PLHZ, do_ldst_PLS_D, false, false, MO_UW)
/* Load Halfword Algebraic */
TRANS(LHA, do_ldst_D, false, false, MO_SW)
TRANS(LHAX, do_ldst_X, false, false, MO_SW)
TRANS(LHAU, do_ldst_D, true, false, MO_SW)
TRANS(LHAXU, do_ldst_X, true, false, MO_SW)
+TRANS(PLHA, do_ldst_PLS_D, false, false, MO_SW)
/* Load Word and Zero */
TRANS(LWZ, do_ldst_D, false, false, MO_UL)
TRANS(LWZX, do_ldst_X, false, false, MO_UL)
TRANS(LWZU, do_ldst_D, true, false, MO_UL)
TRANS(LWZUX, do_ldst_X, true, false, MO_UL)
+TRANS(PLWZ, do_ldst_PLS_D, false, false, MO_UL)
/* Load Word Algebraic */
TRANS64(LWA, do_ldst_D, false, false, MO_SL)
TRANS64(LWAX, do_ldst_X, false, false, MO_SL)
TRANS64(LWAUX, do_ldst_X, true, false, MO_SL)
+TRANS64(PLWA, do_ldst_PLS_D, false, false, MO_SL)
/* Load Doubleword */
TRANS64(LD, do_ldst_D, false, false, MO_Q)
TRANS64(LDX, do_ldst_X, false, false, MO_Q)
TRANS64(LDU, do_ldst_D, true, false, MO_Q)
TRANS64(LDUX, do_ldst_X, true, false, MO_Q)
+TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q)
/*
* Fixed-Point Arithmetic Instructions
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH v5 17/23] target/ppc: Move D/DS/X-form integer stores to decodetree
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
` (15 preceding siblings ...)
2021-05-17 20:50 ` [PATCH v5 16/23] target/ppc: Implement prefixed integer load instructions matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:47 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 18/23] target/ppc: Implement prefixed integer store instructions matheus.ferst
` (6 subsequent siblings)
23 siblings, 1 reply; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
These are all connected by macros in the legacy decoding.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 22 ++++++
target/ppc/translate.c | 85 +---------------------
target/ppc/translate/fixedpoint-impl.c.inc | 24 ++++++
3 files changed, 49 insertions(+), 82 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 70f64c235b..00ec0f4328 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -57,6 +57,28 @@ LDU 111010 ..... ..... ..............01 @DS
LDX 011111 ..... ..... ..... 0000010101 - @X
LDUX 011111 ..... ..... ..... 0000110101 - @X
+### Fixed-Point Store Instructions
+
+STB 100110 ..... ..... ................ @D
+STBU 100111 ..... ..... ................ @D
+STBX 011111 ..... ..... ..... 0011010111 - @X
+STBUX 011111 ..... ..... ..... 0011110111 - @X
+
+STH 101100 ..... ..... ................ @D
+STHU 101101 ..... ..... ................ @D
+STHX 011111 ..... ..... ..... 0110010111 - @X
+STHUX 011111 ..... ..... ..... 0110110111 - @X
+
+STW 100100 ..... ..... ................ @D
+STWU 100101 ..... ..... ................ @D
+STWX 011111 ..... ..... ..... 0010010111 - @X
+STWUX 011111 ..... ..... ..... 0010110111 - @X
+
+STD 111110 ..... ..... ..............00 @DS
+STDU 111110 ..... ..... ..............01 @DS
+STDX 011111 ..... ..... ..... 0010010101 - @X
+STDUX 011111 ..... ..... ..... 0010110101 - @X
+
### Fixed-Point Arithmetic Instructions
ADDI 001110 ..... ..... ................ @D
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index e037efcfe1..bf624edba6 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3385,7 +3385,9 @@ static void glue(gen_qemu_, stop)(DisasContext *ctx, \
tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
}
+#if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY)
GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
+#endif
GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
@@ -3518,52 +3520,6 @@ static void gen_lq(DisasContext *ctx)
#endif
/*** Integer store ***/
-#define GEN_ST(name, stop, opc, type) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_imm_index(ctx, EA, 0); \
- gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
-}
-
-#define GEN_STU(name, stop, opc, type) \
-static void glue(gen_, stop##u)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- if (unlikely(rA(ctx->opcode) == 0)) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- if (type == PPC_64B) \
- gen_addr_imm_index(ctx, EA, 0x03); \
- else \
- gen_addr_imm_index(ctx, EA, 0); \
- gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
-}
-
-#define GEN_STUX(name, stop, opc2, opc3, type) \
-static void glue(gen_, name##ux)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- if (unlikely(rA(ctx->opcode) == 0)) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_reg_index(ctx, EA); \
- gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
-}
-
#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
static void glue(gen_, name##x)(DisasContext *ctx) \
{ \
@@ -3581,19 +3537,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) \
#define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
-#define GEN_STS(name, stop, op, type) \
-GEN_ST(name, stop, op | 0x20, type); \
-GEN_STU(name, stop, op | 0x21, type); \
-GEN_STUX(name, stop, 0x17, op | 0x01, type); \
-GEN_STX(name, stop, 0x17, op | 0x00, type)
-
-/* stb stbu stbux stbx */
-GEN_STS(stb, st8, 0x06, PPC_INTEGER);
-/* sth sthu sthux sthx */
-GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
-/* stw stwu stwux stwx */
-GEN_STS(stw, st32, 0x04, PPC_INTEGER);
-
#define GEN_STEPX(name, stop, opc2, opc3) \
static void glue(gen_, name##epx)(DisasContext *ctx) \
{ \
@@ -3615,8 +3558,6 @@ GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04)
#endif
#if defined(TARGET_PPC64)
-GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
-GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
@@ -8252,31 +8193,11 @@ GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
#endif
-#undef GEN_ST
-#undef GEN_STU
-#undef GEN_STUX
#undef GEN_STX_E
-#undef GEN_STS
-#define GEN_ST(name, stop, opc, type) \
-GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_STU(name, stop, opc, type) \
-GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_STUX(name, stop, opc2, opc3, type) \
-GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
-#define GEN_STS(name, stop, op, type) \
-GEN_ST(name, stop, op | 0x20, type) \
-GEN_STU(name, stop, op | 0x21, type) \
-GEN_STUX(name, stop, 0x17, op | 0x01, type) \
-GEN_STX(name, stop, 0x17, op | 0x00, type)
-
-GEN_STS(stb, st8, 0x06, PPC_INTEGER)
-GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
-GEN_STS(stw, st32, 0x04, PPC_INTEGER)
+
#if defined(TARGET_PPC64)
-GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
-GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 7687f31d6f..adeee33289 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -137,6 +137,30 @@ TRANS64(LDU, do_ldst_D, true, false, MO_Q)
TRANS64(LDUX, do_ldst_X, true, false, MO_Q)
TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q)
+/* Store Byte */
+TRANS(STB, do_ldst_D, false, true, MO_UB)
+TRANS(STBX, do_ldst_X, false, true, MO_UB)
+TRANS(STBU, do_ldst_D, true, true, MO_UB)
+TRANS(STBUX, do_ldst_X, true, true, MO_UB)
+
+/* Store Halfword */
+TRANS(STH, do_ldst_D, false, true, MO_UW)
+TRANS(STHX, do_ldst_X, false, true, MO_UW)
+TRANS(STHU, do_ldst_D, true, true, MO_UW)
+TRANS(STHUX, do_ldst_X, true, true, MO_UW)
+
+/* Store Word */
+TRANS(STW, do_ldst_D, false, true, MO_UL)
+TRANS(STWX, do_ldst_X, false, true, MO_UL)
+TRANS(STWU, do_ldst_D, true, true, MO_UL)
+TRANS(STWUX, do_ldst_X, true, true, MO_UL)
+
+/* Store Doubleword */
+TRANS64(STD, do_ldst_D, false, true, MO_Q)
+TRANS64(STDX, do_ldst_X, false, true, MO_Q)
+TRANS64(STDU, do_ldst_D, true, true, MO_Q)
+TRANS64(STDUX, do_ldst_X, true, true, MO_Q)
+
/*
* Fixed-Point Arithmetic Instructions
*/
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH v5 18/23] target/ppc: Implement prefixed integer store instructions
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
` (16 preceding siblings ...)
2021-05-17 20:50 ` [PATCH v5 17/23] target/ppc: Move D/DS/X-form integer stores to decodetree matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:47 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 19/23] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions matheus.ferst
` (5 subsequent siblings)
23 siblings, 1 reply; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn64.decode | 12 ++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 4 ++++
2 files changed, 16 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 547bd1736f..72c5944a53 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -39,6 +39,18 @@ PLWA 000001 00 0--.-- .................. \
PLD 000001 00 0--.-- .................. \
111001 ..... ..... ................ @PLS_D
+### Fixed-Point Store Instructions
+
+PSTW 000001 10 0--.-- .................. \
+ 100100 ..... ..... ................ @PLS_D
+PSTB 000001 10 0--.-- .................. \
+ 100110 ..... ..... ................ @PLS_D
+PSTH 000001 10 0--.-- .................. \
+ 101100 ..... ..... ................ @PLS_D
+
+PSTD 000001 00 0--.-- .................. \
+ 111101 ..... ..... ................ @PLS_D
+
### Fixed-Point Arithmetic Instructions
PADDI 000001 10 0--.-- .................. \
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index adeee33289..2d2d874146 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -142,24 +142,28 @@ TRANS(STB, do_ldst_D, false, true, MO_UB)
TRANS(STBX, do_ldst_X, false, true, MO_UB)
TRANS(STBU, do_ldst_D, true, true, MO_UB)
TRANS(STBUX, do_ldst_X, true, true, MO_UB)
+TRANS(PSTB, do_ldst_PLS_D, false, true, MO_UB)
/* Store Halfword */
TRANS(STH, do_ldst_D, false, true, MO_UW)
TRANS(STHX, do_ldst_X, false, true, MO_UW)
TRANS(STHU, do_ldst_D, true, true, MO_UW)
TRANS(STHUX, do_ldst_X, true, true, MO_UW)
+TRANS(PSTH, do_ldst_PLS_D, false, true, MO_UW)
/* Store Word */
TRANS(STW, do_ldst_D, false, true, MO_UL)
TRANS(STWX, do_ldst_X, false, true, MO_UL)
TRANS(STWU, do_ldst_D, true, true, MO_UL)
TRANS(STWUX, do_ldst_X, true, true, MO_UL)
+TRANS(PSTW, do_ldst_PLS_D, false, true, MO_UL)
/* Store Doubleword */
TRANS64(STD, do_ldst_D, false, true, MO_Q)
TRANS64(STDX, do_ldst_X, false, true, MO_Q)
TRANS64(STDU, do_ldst_D, true, true, MO_Q)
TRANS64(STDUX, do_ldst_X, true, true, MO_Q)
+TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_Q)
/*
* Fixed-Point Arithmetic Instructions
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH v5 19/23] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
` (17 preceding siblings ...)
2021-05-17 20:50 ` [PATCH v5 18/23] target/ppc: Implement prefixed integer store instructions matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:49 ` David Gibson
2021-05-18 9:48 ` Richard Henderson
2021-05-17 20:50 ` [PATCH v5 20/23] target/ppc: Implement cfuged instruction matheus.ferst
` (4 subsequent siblings)
23 siblings, 2 replies; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implements the following PowerISA v3.1 instructions:
setbc: Set Boolean Condition
setbcr: Set Boolean Condition Reverse
setnbc: Set Negative Boolean Condition
setnbcr: Set Negative Boolean Condition Reverse
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v5:
- Style fix;
- Use tcg_gen_setcondi_tl instead of tcg_gen_movcond_tl.
---
target/ppc/insn32.decode | 10 ++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 23 ++++++++++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 00ec0f4328..bc69c70493 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -26,6 +26,9 @@
&X rt ra rb
@X ...... rt:5 ra:5 rb:5 .......... . &X
+&X_bi rt bi
+@X_bi ...... rt:5 bi:5 ----- .......... - &X_bi
+
### Fixed-Point Load Instructions
LBZ 100010 ..... ..... ................ @D
@@ -83,3 +86,10 @@ STDUX 011111 ..... ..... ..... 0010110101 - @X
ADDI 001110 ..... ..... ................ @D
ADDIS 001111 ..... ..... ................ @D
+
+### Move To/From System Register Instructions
+
+SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
+SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
+SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
+SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 2d2d874146..204848d017 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -204,3 +204,26 @@ static bool trans_PNOP(DisasContext *ctx, arg_PNOP *a)
{
return true;
}
+
+static bool do_set_bool_cond(DisasContext *ctx, arg_X_bi *a, bool neg, bool rev)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ uint32_t mask = 0x08 >> (a->bi & 0x03);
+ TCGCond cond = rev ? TCG_COND_EQ : TCG_COND_NE;
+ TCGv temp = tcg_temp_new();
+
+ tcg_gen_extu_i32_tl(temp, cpu_crf[a->bi >> 2]);
+ tcg_gen_andi_tl(temp, temp, mask);
+ tcg_gen_setcondi_tl(cond, cpu_gpr[a->rt], temp, 0);
+ if(neg) {
+ tcg_gen_neg_tl(cpu_gpr[a->rt], cpu_gpr[a->rt]);
+ }
+ tcg_temp_free(temp);
+
+ return true;
+}
+
+TRANS(SETBC, do_set_bool_cond, false, false)
+TRANS(SETBCR, do_set_bool_cond, false, true)
+TRANS(SETNBC, do_set_bool_cond, true, false)
+TRANS(SETNBCR, do_set_bool_cond, true, true)
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH v5 20/23] target/ppc: Implement cfuged instruction
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
` (18 preceding siblings ...)
2021-05-17 20:50 ` [PATCH v5 19/23] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:51 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 21/23] target/ppc: Implement vcfuged instruction matheus.ferst
` (3 subsequent siblings)
23 siblings, 1 reply; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v5:
- Comments to explain helper_cfuged implementation.
---
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 4 ++
target/ppc/int_helper.c | 62 ++++++++++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 12 +++++
4 files changed, 79 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index ea9f2a236c..c517b9f025 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -46,6 +46,7 @@ DEF_HELPER_4(divwe, tl, env, tl, tl, i32)
DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_3(sraw, tl, env, tl, tl)
+DEF_HELPER_FLAGS_2(cfuged, TCG_CALL_NO_RWG_SE, i64, i64, i64)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_2(cmpeqb, TCG_CALL_NO_RWG_SE, i32, tl, tl)
DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index bc69c70493..d4044d9069 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -87,6 +87,10 @@ STDUX 011111 ..... ..... ..... 0010110101 - @X
ADDI 001110 ..... ..... ................ @D
ADDIS 001111 ..... ..... ................ @D
+## Fixed-Point Logical Instructions
+
+CFUGED 011111 ..... ..... ..... 0011011100 - @X
+
### Move To/From System Register Instructions
SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 41f8477d4b..efa833ef64 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -320,6 +320,68 @@ target_ulong helper_popcntb(target_ulong val)
}
#endif
+uint64_t helper_cfuged(uint64_t src, uint64_t mask)
+{
+ /*
+ * Instead of processing the mask bit-by-bit from the most significant to
+ * the least significant bit, as described in PowerISA, we'll handle it in
+ * blocks of 'n' zeros/ones from LSB to MSB. To avoid the decision to use
+ * ctz or cto, we negate the mask at the end of the loop.
+ */
+ target_ulong m, left = 0, right = 0;
+ unsigned int n, i = 64;
+ bool bit = false; /* tracks if we are processing zeros or ones */
+
+ if (mask == 0 || mask == -1) {
+ return src;
+ }
+
+ /* Processes the mask in blocks, from LSB to MSB */
+ while (i) {
+ /* Find how many bits we should take */
+ n = ctz64(mask);
+ if (n > i) {
+ n = i;
+ }
+
+ /*
+ * Extracts 'n' trailing bits of src and put them on the leading 'n'
+ * bits of 'right' or 'left', pushing down the previously extracted
+ * values.
+ */
+ m = (1ll << n) - 1;
+ if (bit) {
+ right = ror64(right | (src & m), n);
+ } else {
+ left = ror64(left | (src & m), n);
+ }
+
+ /*
+ * Discards the processed bits from 'src' and 'mask'. Note that we are
+ * removing 'n' trailing zeros from 'mask', but the logical shift will
+ * add 'n' leading zeros back, so the population count of 'mask' is kept
+ * the same.
+ */
+ src >>= n;
+ mask >>= n;
+ i -= n;
+ bit = !bit;
+ mask = ~mask;
+ }
+
+ /*
+ * At the end, right was ror'ed ctpop(mask) times. To put it back in place,
+ * we'll shift it more 64-ctpop(mask) times.
+ */
+ if (bit) {
+ n = ctpop64(mask);
+ } else {
+ n = 64 - ctpop64(mask);
+ }
+
+ return left | (right >> n);
+}
+
/*****************************************************************************/
/* PowerPC 601 specific instructions (POWER bridge) */
target_ulong helper_div(CPUPPCState *env, target_ulong arg1, target_ulong arg2)
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 204848d017..4038143efb 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -227,3 +227,15 @@ TRANS(SETBC, do_set_bool_cond, false, false)
TRANS(SETBCR, do_set_bool_cond, false, true)
TRANS(SETNBC, do_set_bool_cond, true, false)
TRANS(SETNBCR, do_set_bool_cond, true, true)
+
+static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+#if defined(TARGET_PPC64)
+ gen_helper_cfuged(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH v5 21/23] target/ppc: Implement vcfuged instruction
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
` (19 preceding siblings ...)
2021-05-17 20:50 ` [PATCH v5 20/23] target/ppc: Implement cfuged instruction matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:52 ` David Gibson
2021-05-18 9:54 ` Richard Henderson
2021-05-17 20:50 ` [PATCH v5 22/23] target/ppc: Move addpcis to decodetree matheus.ferst
` (2 subsequent siblings)
23 siblings, 2 replies; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v5:
- New REQUIRE_ALTIVEC macro;
- REQUIRE_INSNS_FLAGS2.
---
target/ppc/insn32.decode | 7 ++++
target/ppc/translate.c | 1 +
target/ppc/translate/vector-impl.c.inc | 56 ++++++++++++++++++++++++++
3 files changed, 64 insertions(+)
create mode 100644 target/ppc/translate/vector-impl.c.inc
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index d4044d9069..77edf407ab 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -23,6 +23,9 @@
%ds_si 2:s14 !function=times_4
@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
+&VX vrt vra vrb
+@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
+
&X rt ra rb
@X ...... rt:5 ra:5 rb:5 .......... . &X
@@ -97,3 +100,7 @@ SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
+
+## Vector Bit Manipulation Instruction
+
+VCFUGED 000100 ..... ..... ..... 10101001101 @VX
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index bf624edba6..f56ed5866e 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7624,6 +7624,7 @@ static int times_4(DisasContext *ctx, int x)
#include "translate/vmx-impl.c.inc"
#include "translate/vsx-impl.c.inc"
+#include "translate/vector-impl.c.inc"
#include "translate/dfp-impl.c.inc"
diff --git a/target/ppc/translate/vector-impl.c.inc b/target/ppc/translate/vector-impl.c.inc
new file mode 100644
index 0000000000..4f986cf53f
--- /dev/null
+++ b/target/ppc/translate/vector-impl.c.inc
@@ -0,0 +1,56 @@
+/*
+ * Power ISA decode for Vector Facility instructions
+ *
+ * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_ALTIVEC(CTX) \
+ do { \
+ if (unlikely(!(CTX)->altivec_enabled)) { \
+ gen_exception((CTX), POWERPC_EXCP_VPU); \
+ return true; \
+ } \
+ } while (0)
+
+static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
+{
+ TCGv_i64 tgt, src, mask;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_ALTIVEC(ctx);
+
+ tgt = tcg_temp_new_i64();
+ src = tcg_temp_new_i64();
+ mask = tcg_temp_new_i64();
+
+ // centrifuge lower double word
+ get_cpu_vsrl(src, a->vra + 32);
+ get_cpu_vsrl(mask, a->vrb + 32);
+ gen_helper_cfuged(tgt, src, mask);
+ set_cpu_vsrl(a->vrt + 32, tgt);
+
+ // centrifuge higher double word
+ get_cpu_vsrh(src, a->vra + 32);
+ get_cpu_vsrh(mask, a->vrb + 32);
+ gen_helper_cfuged(tgt, src, mask);
+ set_cpu_vsrh(a->vrt + 32, tgt);
+
+ tcg_temp_free_i64(tgt);
+ tcg_temp_free_i64(src);
+ tcg_temp_free_i64(mask);
+
+ return true;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH v5 22/23] target/ppc: Move addpcis to decodetree
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
` (20 preceding siblings ...)
2021-05-17 20:50 ` [PATCH v5 21/23] target/ppc: Implement vcfuged instruction matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:53 ` David Gibson
2021-05-18 9:55 ` Richard Henderson
2021-05-17 20:50 ` [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli " matheus.ferst
2021-05-18 3:58 ` [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions David Gibson
23 siblings, 2 replies; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 6 ++++++
target/ppc/translate.c | 9 ---------
target/ppc/translate/fixedpoint-impl.c.inc | 7 +++++++
3 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 77edf407ab..93e5d44d9e 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -23,6 +23,10 @@
%ds_si 2:s14 !function=times_4
@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
+&DX rt d
+%dx_d 6:s10 16:5 0:1
+@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
+
&VX vrt vra vrb
@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
@@ -90,6 +94,8 @@ STDUX 011111 ..... ..... ..... 0010110101 - @X
ADDI 001110 ..... ..... ................ @D
ADDIS 001111 ..... ..... ................ @D
+ADDPCIS 010011 ..... ..... .......... 00010 . @DX
+
## Fixed-Point Logical Instructions
CFUGED 011111 ..... ..... ..... 0011011100 - @X
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index f56ed5866e..aef01af396 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1865,14 +1865,6 @@ static void gen_addic_(DisasContext *ctx)
gen_op_addic(ctx, 1);
}
-/* addpcis */
-static void gen_addpcis(DisasContext *ctx)
-{
- target_long d = DX(ctx->opcode);
-
- tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16));
-}
-
static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
TCGv arg2, int sign, int compute_ov)
{
@@ -7745,7 +7737,6 @@ GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
-GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 4038143efb..4f257a931c 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -194,6 +194,13 @@ static bool trans_ADDIS(DisasContext *ctx, arg_D *a)
return trans_ADDI(ctx, a);
}
+static bool trans_ADDPCIS(DisasContext *ctx, arg_DX *a)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ tcg_gen_movi_tl(cpu_gpr[a->rt], ctx->base.pc_next + (a->d<<16));
+ return true;
+}
+
static bool trans_INVALID(DisasContext *ctx, arg_INVALID *a)
{
gen_invalid(ctx);
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
` (21 preceding siblings ...)
2021-05-17 20:50 ` [PATCH v5 22/23] target/ppc: Move addpcis to decodetree matheus.ferst
@ 2021-05-17 20:50 ` matheus.ferst
2021-05-18 0:56 ` David Gibson
2021-05-18 10:12 ` Richard Henderson
2021-05-18 3:58 ` [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions David Gibson
23 siblings, 2 replies; 57+ messages in thread
From: matheus.ferst @ 2021-05-17 20:50 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 14 ++++++
target/ppc/translate.c | 52 ----------------------
target/ppc/translate/fixedpoint-impl.c.inc | 31 +++++++++++++
3 files changed, 45 insertions(+), 52 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 93e5d44d9e..9fd8d6b817 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -20,6 +20,10 @@
&D rt ra si:int64_t
@D ...... rt:5 ra:5 si:s16 &D
+&D_bf bf l:bool ra imm
+@D_bfs ...... bf:3 - l:1 ra:5 imm:s16 &D_bf
+@D_bfu ...... bf:3 - l:1 ra:5 imm:16 &D_bf
+
%ds_si 2:s14 !function=times_4
@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
@@ -36,6 +40,9 @@
&X_bi rt bi
@X_bi ...... rt:5 bi:5 ----- .......... - &X_bi
+&X_bfl bf l:bool ra rb
+@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl
+
### Fixed-Point Load Instructions
LBZ 100010 ..... ..... ................ @D
@@ -89,6 +96,13 @@ STDU 111110 ..... ..... ..............01 @DS
STDX 011111 ..... ..... ..... 0010010101 - @X
STDUX 011111 ..... ..... ..... 0010110101 - @X
+### Fixed-Point Compare Instructions
+
+CMP 011111 ... - . ..... ..... 0000000000 - @X_bfl
+CMPL 011111 ... - . ..... ..... 0000100000 - @X_bfl
+CMPI 001011 ... - . ..... ................ @D_bfs
+CMPLI 001010 ... - . ..... ................ @D_bfu
+
### Fixed-Point Arithmetic Instructions
ADDI 001110 ..... ..... ................ @D
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index aef01af396..3fe58d0386 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1575,54 +1575,6 @@ static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
}
}
-/* cmp */
-static void gen_cmp(DisasContext *ctx)
-{
- if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
- gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
- 1, crfD(ctx->opcode));
- } else {
- gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
- 1, crfD(ctx->opcode));
- }
-}
-
-/* cmpi */
-static void gen_cmpi(DisasContext *ctx)
-{
- if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
- gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
- 1, crfD(ctx->opcode));
- } else {
- gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
- 1, crfD(ctx->opcode));
- }
-}
-
-/* cmpl */
-static void gen_cmpl(DisasContext *ctx)
-{
- if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
- gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
- 0, crfD(ctx->opcode));
- } else {
- gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
- 0, crfD(ctx->opcode));
- }
-}
-
-/* cmpli */
-static void gen_cmpli(DisasContext *ctx)
-{
- if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
- gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
- 0, crfD(ctx->opcode));
- } else {
- gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
- 0, crfD(ctx->opcode));
- }
-}
-
/* cmprb - range comparison: isupper, isaplha, islower*/
static void gen_cmprb(DisasContext *ctx)
{
@@ -7725,10 +7677,6 @@ GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310),
GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310),
#endif
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
-GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
-GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
-GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
-GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
#if defined(TARGET_PPC64)
GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
#endif
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 4f257a931c..49c8993333 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -165,6 +165,37 @@ TRANS64(STDU, do_ldst_D, true, true, MO_Q)
TRANS64(STDUX, do_ldst_X, true, true, MO_Q)
TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_Q)
+/*
+ * Fixed-Point Compare Instructions
+ */
+
+static bool do_cmp_X(DisasContext *ctx, arg_X_bfl *a, bool s)
+{
+ REQUIRE_INSNS_FLAGS(ctx, INTEGER);
+ if(a->l && (ctx->insns_flags & PPC_64B)) {
+ gen_op_cmp(cpu_gpr[a->ra], cpu_gpr[a->rb], s, a->bf);
+ } else {
+ gen_op_cmp32(cpu_gpr[a->ra], cpu_gpr[a->rb], s, a->bf);
+ }
+ return true;
+}
+
+static bool do_cmp_D(DisasContext *ctx, arg_D_bf *a, bool s)
+{
+ REQUIRE_INSNS_FLAGS(ctx, INTEGER);
+ if(a->l && (ctx->insns_flags & PPC_64B)) {
+ gen_op_cmp(cpu_gpr[a->ra], tcg_constant_tl(a->imm), s, a->bf);
+ } else {
+ gen_op_cmp32(cpu_gpr[a->ra], tcg_constant_tl(a->imm), s, a->bf);
+ }
+ return true;
+}
+
+TRANS(CMP, do_cmp_X, true);
+TRANS(CMPL, do_cmp_X, false);
+TRANS(CMPI, do_cmp_D, true);
+TRANS(CMPLI, do_cmp_D, false);
+
/*
* Fixed-Point Arithmetic Instructions
*/
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread
* Re: [PATCH v5 01/23] target/ppc: Introduce gen_icount_io_start
2021-05-17 20:50 ` [PATCH v5 01/23] target/ppc: Introduce gen_icount_io_start matheus.ferst
@ 2021-05-18 0:13 ` David Gibson
0 siblings, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:13 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 12297 bytes --]
On Mon, May 17, 2021 at 05:50:03PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> Create a function to handle the details for interacting with icount.
>
> Force the exit from the tb via DISAS_TOO_MANY, which allows chaining
> to the next tb, where the code emitted for gen_tb_start() will
> determine if we must exit. We can thus remove any matching
> conditional call to gen_stop_exception.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/translate.c | 174 +++++++++--------------------------------
> 1 file changed, 39 insertions(+), 135 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index d51a1913a7..060ef83bc0 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -304,6 +304,20 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
> ctx->base.is_jmp = DISAS_NORETURN;
> }
>
> +static void gen_icount_io_start(DisasContext *ctx)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + /*
> + * An I/O instruction must be last in the TB.
> + * Chain to the next TB, and let the code from gen_tb_start
> + * decide if we need to return to the main loop.
> + * Doing this first also allows this value to be overridden.
> + */
> + ctx->base.is_jmp = DISAS_TOO_MANY;
> + }
> +}
> +
> /*
> * Tells the caller what is the appropriate exception to generate and prepares
> * SPR registers for this exception.
> @@ -540,24 +554,14 @@ void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
> #if !defined(CONFIG_USER_ONLY)
> void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
> #endif
>
> @@ -565,24 +569,14 @@ void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
> /* Time base */
> void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
> @@ -598,24 +592,14 @@ void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
> #if !defined(CONFIG_USER_ONLY)
> void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
> @@ -631,80 +615,45 @@ void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
> #if defined(TARGET_PPC64)
> void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> /* HDECR */
> void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> #endif
> @@ -912,71 +861,41 @@ void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
> #if !defined(CONFIG_USER_ONLY)
> void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_store_spr(sprn, cpu_gpr[gprn]);
> gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
> /* We must stop translation as we may have rebooted */
> gen_stop_exception(ctx);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
> #endif
>
> @@ -2860,18 +2779,13 @@ static void gen_darn(DisasContext *ctx)
> if (l > 2) {
> tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
> } else {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> if (l == 0) {
> gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
> } else {
> /* Return 64-bit random for both CRN and RRN */
> gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
> }
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
> }
> #endif
> @@ -5013,9 +4927,7 @@ static void gen_rfi(DisasContext *ctx)
> }
> /* Restore CPU state */
> CHK_SV;
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_update_cfar(ctx, ctx->cia);
> gen_helper_rfi(cpu_env);
> ctx->base.is_jmp = DISAS_EXIT;
> @@ -5030,9 +4942,7 @@ static void gen_rfid(DisasContext *ctx)
> #else
> /* Restore CPU state */
> CHK_SV;
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_update_cfar(ctx, ctx->cia);
> gen_helper_rfid(cpu_env);
> ctx->base.is_jmp = DISAS_EXIT;
> @@ -5047,9 +4957,7 @@ static void gen_rfscv(DisasContext *ctx)
> #else
> /* Restore CPU state */
> CHK_SV;
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_update_cfar(ctx, ctx->cia);
> gen_helper_rfscv(cpu_env);
> ctx->base.is_jmp = DISAS_EXIT;
> @@ -5379,9 +5287,7 @@ static void gen_mtmsrd(DisasContext *ctx)
> CHK_SV;
>
> #if !defined(CONFIG_USER_ONLY)
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> if (ctx->opcode & 0x00010000) {
> /* L=1 form only updates EE and RI */
> TCGv t0 = tcg_temp_new();
> @@ -5416,9 +5322,7 @@ static void gen_mtmsr(DisasContext *ctx)
> CHK_SV;
>
> #if !defined(CONFIG_USER_ONLY)
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> if (ctx->opcode & 0x00010000) {
> /* L=1 form only updates EE and RI */
> TCGv t0 = tcg_temp_new();
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 02/23] target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE
2021-05-17 20:50 ` [PATCH v5 02/23] target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE matheus.ferst
@ 2021-05-18 0:14 ` David Gibson
0 siblings, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:14 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 5787 bytes --]
On Mon, May 17, 2021 at 05:50:04PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> Remove the synthetic "exception" after no more uses.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> linux-user/ppc/cpu_loop.c | 3 ---
> target/ppc/cpu.h | 1 -
> target/ppc/translate.c | 24 +++++++-----------------
> 3 files changed, 7 insertions(+), 21 deletions(-)
>
> diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c
> index 4a0f6c8dc2..fe526693d2 100644
> --- a/linux-user/ppc/cpu_loop.c
> +++ b/linux-user/ppc/cpu_loop.c
> @@ -423,9 +423,6 @@ void cpu_loop(CPUPPCState *env)
> cpu_abort(cs, "Maintenance exception while in user mode. "
> "Aborting\n");
> break;
> - case POWERPC_EXCP_STOP: /* stop translation */
> - /* We did invalidate the instruction cache. Go on */
> - break;
> case POWERPC_EXCP_BRANCH: /* branch instruction: */
> /* We just stopped because of a branch. Go on */
> break;
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 99ee1e09b2..9e38df685d 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -132,7 +132,6 @@ enum {
> /* EOL */
> POWERPC_EXCP_NB = 103,
> /* QEMU exceptions: used internally during code translation */
> - POWERPC_EXCP_STOP = 0x200, /* stop translation */
> POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
> /* QEMU exceptions: special cases we want to stop translation */
> POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 060ef83bc0..f57b67be5f 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -369,13 +369,6 @@ static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
> gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
> }
>
> -/* Stop translation */
> -static inline void gen_stop_exception(DisasContext *ctx)
> -{
> - gen_update_nip(ctx, ctx->base.pc_next);
> - ctx->exception = POWERPC_EXCP_STOP;
> -}
> -
> /*****************************************************************************/
> /* SPR READ/WRITE CALLBACKS */
>
> @@ -829,7 +822,7 @@ void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
> {
> gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
> /* Must stop the translation as endianness may have changed */
> - gen_stop_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT_UPDATE;
> }
> #endif
>
> @@ -877,7 +870,7 @@ void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
> gen_store_spr(sprn, cpu_gpr[gprn]);
> gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
> /* We must stop translation as we may have rebooted */
> - gen_stop_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT_UPDATE;
> }
>
> void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
> @@ -4080,7 +4073,7 @@ static void gen_isync(DisasContext *ctx)
> gen_check_tlb_flush(ctx, false);
> }
> tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
> - gen_stop_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT_UPDATE;
> }
>
> #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
> @@ -5312,7 +5305,7 @@ static void gen_mtmsrd(DisasContext *ctx)
> gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
> }
> /* Must stop the translation as machine state (may have) changed */
> - gen_stop_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT_UPDATE;
> #endif /* !defined(CONFIG_USER_ONLY) */
> }
> #endif /* defined(TARGET_PPC64) */
> @@ -5355,7 +5348,7 @@ static void gen_mtmsr(DisasContext *ctx)
> tcg_temp_free(msr);
> }
> /* Must stop the translation as machine state (may have) changed */
> - gen_stop_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT_UPDATE;
> #endif
> }
>
> @@ -7492,7 +7485,7 @@ static void gen_wrtee(DisasContext *ctx)
> * Stop translation to have a chance to raise an exception if we
> * just set msr_ee to 1
> */
> - gen_stop_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT_UPDATE;
> #endif /* defined(CONFIG_USER_ONLY) */
> }
>
> @@ -7506,7 +7499,7 @@ static void gen_wrteei(DisasContext *ctx)
> if (ctx->opcode & 0x00008000) {
> tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
> /* Stop translation to have a chance to raise an exception */
> - gen_stop_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT_UPDATE;
> } else {
> tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
> }
> @@ -9128,9 +9121,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> case POWERPC_EXCP_BRANCH:
> ctx->base.is_jmp = DISAS_NORETURN;
> break;
> - case POWERPC_EXCP_STOP:
> - ctx->base.is_jmp = DISAS_EXIT;
> - break;
> default:
> /* Every other ctx->exception should have set NORETURN. */
> g_assert_not_reached();
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 03/23] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN
2021-05-17 20:50 ` [PATCH v5 03/23] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN matheus.ferst
@ 2021-05-18 0:15 ` David Gibson
0 siblings, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:15 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 4429 bytes --]
On Mon, May 17, 2021 at 05:50:05PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> The translation of branch instructions always results in exit from
> the TB. Remove the synthetic "exception" after no more uses.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> linux-user/ppc/cpu_loop.c | 3 ---
> target/ppc/cpu.h | 2 --
> target/ppc/translate.c | 8 ++------
> 3 files changed, 2 insertions(+), 11 deletions(-)
>
> diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c
> index fe526693d2..fa91ea0eed 100644
> --- a/linux-user/ppc/cpu_loop.c
> +++ b/linux-user/ppc/cpu_loop.c
> @@ -423,9 +423,6 @@ void cpu_loop(CPUPPCState *env)
> cpu_abort(cs, "Maintenance exception while in user mode. "
> "Aborting\n");
> break;
> - case POWERPC_EXCP_BRANCH: /* branch instruction: */
> - /* We just stopped because of a branch. Go on */
> - break;
> case POWERPC_EXCP_SYSCALL_USER:
> /* system call in user-mode emulation */
> /* WARNING:
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 9e38df685d..cab33a3680 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -131,8 +131,6 @@ enum {
> POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception */
> /* EOL */
> POWERPC_EXCP_NB = 103,
> - /* QEMU exceptions: used internally during code translation */
> - POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
> /* QEMU exceptions: special cases we want to stop translation */
> POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
> };
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index f57b67be5f..d019454550 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -4692,7 +4692,6 @@ static void gen_b(DisasContext *ctx)
> {
> target_ulong li, target;
>
> - ctx->exception = POWERPC_EXCP_BRANCH;
> /* sign extend LI */
> li = LI(ctx->opcode);
> li = (li ^ 0x02000000) - 0x02000000;
> @@ -4706,6 +4705,7 @@ static void gen_b(DisasContext *ctx)
> }
> gen_update_cfar(ctx, ctx->cia);
> gen_goto_tb(ctx, 0, target);
> + ctx->base.is_jmp = DISAS_NORETURN;
> }
>
> #define BCOND_IM 0
> @@ -4718,7 +4718,6 @@ static void gen_bcond(DisasContext *ctx, int type)
> uint32_t bo = BO(ctx->opcode);
> TCGLabel *l1;
> TCGv target;
> - ctx->exception = POWERPC_EXCP_BRANCH;
>
> if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
> target = tcg_temp_local_new();
> @@ -4825,6 +4824,7 @@ static void gen_bcond(DisasContext *ctx, int type)
> gen_set_label(l1);
> gen_goto_tb(ctx, 1, ctx->base.pc_next);
> }
> + ctx->base.is_jmp = DISAS_NORETURN;
> }
>
> static void gen_bc(DisasContext *ctx)
> @@ -9102,7 +9102,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> /* Check trace mode exceptions */
> if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
> (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
> - ctx->exception != POWERPC_EXCP_BRANCH &&
> ctx->base.is_jmp != DISAS_NORETURN)) {
> uint32_t excp = gen_prep_dbgex(ctx);
> gen_exception_nip(ctx, excp, ctx->base.pc_next);
> @@ -9118,9 +9117,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> switch (ctx->exception) {
> case POWERPC_EXCP_NONE:
> break;
> - case POWERPC_EXCP_BRANCH:
> - ctx->base.is_jmp = DISAS_NORETURN;
> - break;
> default:
> /* Every other ctx->exception should have set NORETURN. */
> g_assert_not_reached();
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 04/23] target/ppc: Remove DisasContext.exception
2021-05-17 20:50 ` [PATCH v5 04/23] target/ppc: Remove DisasContext.exception matheus.ferst
@ 2021-05-18 0:17 ` David Gibson
0 siblings, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:17 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 4281 bytes --]
On Mon, May 17, 2021 at 05:50:06PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> Now that we have removed all of the fake exceptions, and all real
> exceptions exit via DISAS_NORETURN, we can remove this field.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/translate.c | 30 ++++--------------------------
> 1 file changed, 4 insertions(+), 26 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index d019454550..80cd11b3f8 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -159,7 +159,6 @@ struct DisasContext {
> DisasContextBase base;
> target_ulong cia; /* current instruction address */
> uint32_t opcode;
> - uint32_t exception;
> /* Routine used to access memory */
> bool pr, hv, dr, le_mode;
> bool lazy_tlb_flush;
> @@ -261,15 +260,12 @@ static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
> * These are all synchronous exceptions, we set the PC back to the
> * faulting instruction
> */
> - if (ctx->exception == POWERPC_EXCP_NONE) {
> - gen_update_nip(ctx, ctx->cia);
> - }
> + gen_update_nip(ctx, ctx->cia);
> t0 = tcg_const_i32(excp);
> t1 = tcg_const_i32(error);
> gen_helper_raise_exception_err(cpu_env, t0, t1);
> tcg_temp_free_i32(t0);
> tcg_temp_free_i32(t1);
> - ctx->exception = excp;
> ctx->base.is_jmp = DISAS_NORETURN;
> }
>
> @@ -281,13 +277,10 @@ static void gen_exception(DisasContext *ctx, uint32_t excp)
> * These are all synchronous exceptions, we set the PC back to the
> * faulting instruction
> */
> - if (ctx->exception == POWERPC_EXCP_NONE) {
> - gen_update_nip(ctx, ctx->cia);
> - }
> + gen_update_nip(ctx, ctx->cia);
> t0 = tcg_const_i32(excp);
> gen_helper_raise_exception(cpu_env, t0);
> tcg_temp_free_i32(t0);
> - ctx->exception = excp;
> ctx->base.is_jmp = DISAS_NORETURN;
> }
>
> @@ -300,7 +293,6 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
> t0 = tcg_const_i32(excp);
> gen_helper_raise_exception(cpu_env, t0);
> tcg_temp_free_i32(t0);
> - ctx->exception = excp;
> ctx->base.is_jmp = DISAS_NORETURN;
> }
>
> @@ -4993,13 +4985,10 @@ static void gen_scv(DisasContext *ctx)
> uint32_t lev = (ctx->opcode >> 5) & 0x7F;
>
> /* Set the PC back to the faulting instruction. */
> - if (ctx->exception == POWERPC_EXCP_NONE) {
> - gen_update_nip(ctx, ctx->cia);
> - }
> + gen_update_nip(ctx, ctx->cia);
> gen_helper_scv(cpu_env, tcg_constant_i32(lev));
>
> - /* This need not be exact, just not POWERPC_EXCP_NONE */
> - ctx->exception = POWERPC_SYSCALL_VECTORED;
> + ctx->base.is_jmp = DISAS_NORETURN;
> }
> #endif
> #endif
> @@ -9005,7 +8994,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> uint32_t hflags = ctx->base.tb->flags;
> int bound;
>
> - ctx->exception = POWERPC_EXCP_NONE;
> ctx->spr_cb = env->spr_cb;
> ctx->pr = (hflags >> HFLAGS_PR) & 1;
> ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7;
> @@ -9112,16 +9100,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode),
> opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
> }
> -
> - if (ctx->base.is_jmp == DISAS_NEXT) {
> - switch (ctx->exception) {
> - case POWERPC_EXCP_NONE:
> - break;
> - default:
> - /* Every other ctx->exception should have set NORETURN. */
> - g_assert_not_reached();
> - }
> - }
> }
>
> static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 05/23] target/ppc: Move single-step check to ppc_tr_tb_stop
2021-05-17 20:50 ` [PATCH v5 05/23] target/ppc: Move single-step check to ppc_tr_tb_stop matheus.ferst
@ 2021-05-18 0:19 ` David Gibson
0 siblings, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:19 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 4168 bytes --]
On Mon, May 17, 2021 at 05:50:07PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> When single-stepping, force max_insns to 1 in init_disas
> so that we exit the translation loop immediately.
>
> Combine the single-step checks in tb_stop, and give the
> gdb exception priority over the cpu exception, just as
> we already do in gen_lookup_and_goto_ptr.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/translate.c | 33 +++++++++++++++++++--------------
> 1 file changed, 19 insertions(+), 14 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 80cd11b3f8..05e3c0417a 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -8992,7 +8992,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
> CPUPPCState *env = cs->env_ptr;
> uint32_t hflags = ctx->base.tb->flags;
> - int bound;
>
> ctx->spr_cb = env->spr_cb;
> ctx->pr = (hflags >> HFLAGS_PR) & 1;
> @@ -9032,8 +9031,12 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
> }
>
> - bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
> - ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
> + if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP)) {
> + ctx->base.max_insns = 1;
> + } else {
> + int bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
> + ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
> + }
> }
>
> static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
> @@ -9087,14 +9090,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> handler->count++;
> #endif
>
> - /* Check trace mode exceptions */
> - if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
> - (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
> - ctx->base.is_jmp != DISAS_NORETURN)) {
> - uint32_t excp = gen_prep_dbgex(ctx);
> - gen_exception_nip(ctx, excp, ctx->base.pc_next);
> - }
> -
> if (tcg_check_temp_count()) {
> qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked "
> "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode),
> @@ -9107,6 +9102,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
> DisasJumpType is_jmp = ctx->base.is_jmp;
> target_ulong nip = ctx->base.pc_next;
> + int sse;
>
> if (is_jmp == DISAS_NORETURN) {
> /* We have already exited the TB. */
> @@ -9114,7 +9110,8 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
> }
>
> /* Honor single stepping. */
> - if (unlikely(ctx->base.singlestep_enabled)) {
> + sse = ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP);
> + if (unlikely(sse)) {
> switch (is_jmp) {
> case DISAS_TOO_MANY:
> case DISAS_EXIT_UPDATE:
> @@ -9127,8 +9124,16 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
> default:
> g_assert_not_reached();
> }
> - gen_debug_exception(ctx);
> - return;
> +
> + if (sse & GDBSTUB_SINGLE_STEP) {
> + gen_debug_exception(ctx);
> + return;
> + }
> + /* else CPU_SINGLE_STEP... */
> + if (nip <= 0x100 || nip > 0xf00) {
> + gen_exception(ctx, gen_prep_dbgex(ctx));
> + return;
> + }
> }
>
> switch (is_jmp) {
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 06/23] target/ppc: Tidy exception vs exit_tb
2021-05-17 20:50 ` [PATCH v5 06/23] target/ppc: Tidy exception vs exit_tb matheus.ferst
@ 2021-05-18 0:19 ` David Gibson
0 siblings, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:19 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 1299 bytes --]
On Mon, May 17, 2021 at 05:50:08PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> We do not need to emit an exit_tb after an exception,
> as the latter will exit via longjmp.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/translate.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 05e3c0417a..e68152810e 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -4648,8 +4648,9 @@ static void gen_lookup_and_goto_ptr(DisasContext *ctx)
> } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) {
> uint32_t excp = gen_prep_dbgex(ctx);
> gen_exception(ctx, excp);
> + } else {
> + tcg_gen_exit_tb(NULL, 0);
> }
> - tcg_gen_exit_tb(NULL, 0);
> } else {
> tcg_gen_lookup_and_goto_ptr();
> }
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 07/23] target/ppc: Mark helper_raise_exception* as noreturn
2021-05-17 20:50 ` [PATCH v5 07/23] target/ppc: Mark helper_raise_exception* as noreturn matheus.ferst
@ 2021-05-18 0:20 ` David Gibson
0 siblings, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:20 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 1254 bytes --]
On Mon, May 17, 2021 at 05:50:09PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/helper.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index 513066d54d..ea9f2a236c 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -1,5 +1,5 @@
> -DEF_HELPER_FLAGS_3(raise_exception_err, TCG_CALL_NO_WG, void, env, i32, i32)
> -DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, void, env, i32)
> +DEF_HELPER_FLAGS_3(raise_exception_err, TCG_CALL_NO_WG, noreturn, env, i32, i32)
> +DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32)
> DEF_HELPER_FLAGS_4(tw, TCG_CALL_NO_WG, void, env, tl, tl, i32)
> #if defined(TARGET_PPC64)
> DEF_HELPER_FLAGS_4(td, TCG_CALL_NO_WG, void, env, tl, tl, i32)
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 08/23] target/ppc: Use translator_loop_temp_check
2021-05-17 20:50 ` [PATCH v5 08/23] target/ppc: Use translator_loop_temp_check matheus.ferst
@ 2021-05-18 0:20 ` David Gibson
0 siblings, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:20 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 1485 bytes --]
On Mon, May 17, 2021 at 05:50:10PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> The special logging is unnecessary. It will have been done
> immediately before in the log file.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
> Reviewed-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/translate.c | 6 +-----
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index e68152810e..ea200f9637 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -9091,11 +9091,7 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> handler->count++;
> #endif
>
> - if (tcg_check_temp_count()) {
> - qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked "
> - "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode),
> - opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
> - }
> + translator_loop_temp_check(&ctx->base);
> }
>
> static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 09/23] target/ppc: Introduce macros to check isa extensions
2021-05-17 20:50 ` [PATCH v5 09/23] target/ppc: Introduce macros to check isa extensions matheus.ferst
@ 2021-05-18 0:21 ` David Gibson
0 siblings, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:21 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 2219 bytes --]
On Mon, May 17, 2021 at 05:50:11PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> These will be used by the decodetree trans_* functions
> to early-exit when the instruction set is not enabled.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/translate.c | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index ea200f9637..dc0f5fafc2 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -7750,6 +7750,32 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high)
> tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
> }
>
> +/*
> + * Helpers for trans_* functions to check for specific insns flags.
> + * Use token pasting to ensure that we use the proper flag with the
> + * proper variable.
> + */
> +#define REQUIRE_INSNS_FLAGS(CTX, NAME) \
> + do { \
> + if (((CTX)->insns_flags & PPC_##NAME) == 0) { \
> + return false; \
> + } \
> + } while (0)
> +
> +#define REQUIRE_INSNS_FLAGS2(CTX, NAME) \
> + do { \
> + if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \
> + return false; \
> + } \
> + } while (0)
> +
> +/* Then special-case the check for 64-bit so that we elide code for ppc32. */
> +#if TARGET_LONG_BITS == 32
> +# define REQUIRE_64BIT(CTX) return false
> +#else
> +# define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B)
> +#endif
> +
> #include "translate/fp-impl.c.inc"
>
> #include "translate/vmx-impl.c.inc"
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 10/23] target/ppc: Move page crossing check to ppc_tr_translate_insn
2021-05-17 20:50 ` [PATCH v5 10/23] target/ppc: Move page crossing check to ppc_tr_translate_insn matheus.ferst
@ 2021-05-18 0:23 ` David Gibson
0 siblings, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:23 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 1693 bytes --]
On Mon, May 17, 2021 at 05:50:12PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> With prefixed instructions, the number of instructions
> remaining until the page crossing is no longer constant.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/translate.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index dc0f5fafc2..b1873d2dcc 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -9060,9 +9060,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
>
> if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP)) {
> ctx->base.max_insns = 1;
> - } else {
> - int bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
> - ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
> }
> }
>
> @@ -9117,6 +9114,11 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> handler->count++;
> #endif
>
> + /* End the TB when crossing a page boundary. */
> + if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) {
> + ctx->base.is_jmp = DISAS_TOO_MANY;
> + }
> +
> translator_loop_temp_check(&ctx->base);
> }
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 11/23] target/ppc: Add infrastructure for prefixed insns
2021-05-17 20:50 ` [PATCH v5 11/23] target/ppc: Add infrastructure for prefixed insns matheus.ferst
@ 2021-05-18 0:25 ` David Gibson
0 siblings, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:25 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 8390 bytes --]
On Mon, May 17, 2021 at 05:50:13PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/cpu.h | 1 +
> target/ppc/insn32.decode | 18 ++++++++++++
> target/ppc/insn64.decode | 18 ++++++++++++
> target/ppc/meson.build | 9 ++++++
> target/ppc/translate.c | 34 +++++++++++++++++++---
> target/ppc/translate/fixedpoint-impl.c.inc | 18 ++++++++++++
> 6 files changed, 94 insertions(+), 4 deletions(-)
> create mode 100644 target/ppc/insn32.decode
> create mode 100644 target/ppc/insn64.decode
> create mode 100644 target/ppc/translate/fixedpoint-impl.c.inc
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index cab33a3680..351fcdf5f8 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -144,6 +144,7 @@ enum {
> POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
> POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
> POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
> + POWERPC_EXCP_ALIGN_INSN = 0x07, /* Pref. insn x-ing 64-byte boundary */
> /* Exception subtypes for POWERPC_EXCP_PROGRAM */
> /* FP exceptions */
> POWERPC_EXCP_FP = 0x10,
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> new file mode 100644
> index 0000000000..a3a8ae06bf
> --- /dev/null
> +++ b/target/ppc/insn32.decode
> @@ -0,0 +1,18 @@
> +#
> +# Power ISA decode for 32-bit insns (opcode space 0)
> +#
> +# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
> +#
> +# This library is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU Lesser General Public
> +# License as published by the Free Software Foundation; either
> +# version 2.1 of the License, or (at your option) any later version.
> +#
> +# This library is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> +# Lesser General Public License for more details.
> +#
> +# You should have received a copy of the GNU Lesser General Public
> +# License along with this library; if not, see <http://www.gnu.org/licenses/>.
> +#
> diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
> new file mode 100644
> index 0000000000..a38b1f84dc
> --- /dev/null
> +++ b/target/ppc/insn64.decode
> @@ -0,0 +1,18 @@
> +#
> +# Power ISA decode for 64-bit prefixed insns (opcode space 0 and 1)
> +#
> +# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
> +#
> +# This library is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU Lesser General Public
> +# License as published by the Free Software Foundation; either
> +# version 2.1 of the License, or (at your option) any later version.
> +#
> +# This library is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> +# Lesser General Public License for more details.
> +#
> +# You should have received a copy of the GNU Lesser General Public
> +# License along with this library; if not, see <http://www.gnu.org/licenses/>.
> +#
> diff --git a/target/ppc/meson.build b/target/ppc/meson.build
> index d1aa7d5d39..512e3a0288 100644
> --- a/target/ppc/meson.build
> +++ b/target/ppc/meson.build
> @@ -17,6 +17,15 @@ ppc_ss.add(files(
>
> ppc_ss.add(libdecnumber)
>
> +gen = [
> + decodetree.process('insn32.decode',
> + extra_args: '--static-decode=decode_insn32'),
> + decodetree.process('insn64.decode',
> + extra_args: ['--static-decode=decode_insn64',
> + '--insnwidth=64']),
> +]
> +ppc_ss.add(gen)
> +
> ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
> ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c'))
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index b1873d2dcc..64d6acb078 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -7776,6 +7776,10 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high)
> # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B)
> #endif
>
> +#include "decode-insn32.c.inc"
> +#include "decode-insn64.c.inc"
> +#include "translate/fixedpoint-impl.c.inc"
> +
> #include "translate/fp-impl.c.inc"
>
> #include "translate/vmx-impl.c.inc"
> @@ -9089,11 +9093,18 @@ static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
> return true;
> }
>
> +static bool is_prefix_insn(DisasContext *ctx, uint32_t insn)
> +{
> + REQUIRE_INSNS_FLAGS2(ctx, ISA310);
> + return opc1(insn) == 1;
> +}
> +
> static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> {
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
> PowerPCCPU *cpu = POWERPC_CPU(cs);
> CPUPPCState *env = cs->env_ptr;
> + target_ulong pc;
> uint32_t insn;
> bool ok;
>
> @@ -9101,11 +9112,26 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
> ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
>
> - ctx->cia = ctx->base.pc_next;
> - insn = translator_ldl_swap(env, ctx->base.pc_next, need_byteswap(ctx));
> - ctx->base.pc_next += 4;
> + ctx->cia = pc = ctx->base.pc_next;
> + insn = translator_ldl_swap(env, pc, need_byteswap(ctx));
> + ctx->base.pc_next = pc += 4;
>
> - ok = decode_legacy(cpu, ctx, insn);
> + if (!is_prefix_insn(ctx, insn)) {
> + ok = (decode_insn32(ctx, insn) ||
> + decode_legacy(cpu, ctx, insn));
> + } else if ((pc & 63) == 0) {
> + /*
> + * Power v3.1, section 1.9 Exceptions:
> + * attempt to execute a prefixed instruction that crosses a
> + * 64-byte address boundary (system alignment error).
> + */
> + gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN);
> + ok = true;
> + } else {
> + uint32_t insn2 = translator_ldl_swap(env, pc, need_byteswap(ctx));
> + ctx->base.pc_next = pc += 4;
> + ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn));
> + }
> if (!ok) {
> gen_invalid(ctx);
> }
> diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
> new file mode 100644
> index 0000000000..be75085cee
> --- /dev/null
> +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> @@ -0,0 +1,18 @@
> +/*
> + * Power ISA decode for Fixed-Point Facility instructions
> + *
> + * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 12/23] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI
2021-05-17 20:50 ` [PATCH v5 12/23] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI matheus.ferst
@ 2021-05-18 0:35 ` David Gibson
0 siblings, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:35 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 6077 bytes --]
On Mon, May 17, 2021 at 05:50:14PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/insn32.decode | 8 ++++
> target/ppc/insn64.decode | 12 ++++++
> target/ppc/translate.c | 29 --------------
> target/ppc/translate/fixedpoint-impl.c.inc | 44 ++++++++++++++++++++++
> 4 files changed, 64 insertions(+), 29 deletions(-)
>
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index a3a8ae06bf..e7c062d8b4 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -16,3 +16,11 @@
> # You should have received a copy of the GNU Lesser General Public
> # License along with this library; if not, see <http://www.gnu.org/licenses/>.
> #
> +
> +&D rt ra si:int64_t
> +@D ...... rt:5 ra:5 si:s16 &D
> +
> +### Fixed-Point Arithmetic Instructions
> +
> +ADDI 001110 ..... ..... ................ @D
> +ADDIS 001111 ..... ..... ................ @D
> diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
> index a38b1f84dc..1965088915 100644
> --- a/target/ppc/insn64.decode
> +++ b/target/ppc/insn64.decode
> @@ -16,3 +16,15 @@
> # You should have received a copy of the GNU Lesser General Public
> # License along with this library; if not, see <http://www.gnu.org/licenses/>.
> #
> +
> +# Format MLS:D and 8LS:D
> +&PLS_D rt ra si:int64_t r:bool
> +%pls_si 32:s18 0:16
> +@PLS_D ...... .. ... r:1 .. .................. \
> + ...... rt:5 ra:5 ................ \
> + &PLS_D si=%pls_si
> +
> +### Fixed-Point Arithmetic Instructions
> +
> +PADDI 000001 10 0--.-- .................. \
> + 001110 ..... ..... ................ @PLS_D
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 64d6acb078..5bf9001141 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -1846,19 +1846,6 @@ GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0);
> /* addze addze. addzeo addzeo.*/
> GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0)
> GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
> -/* addi */
> -static void gen_addi(DisasContext *ctx)
> -{
> - target_long simm = SIMM(ctx->opcode);
> -
> - if (rA(ctx->opcode) == 0) {
> - /* li case */
> - tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
> - } else {
> - tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
> - cpu_gpr[rA(ctx->opcode)], simm);
> - }
> -}
> /* addic addic.*/
> static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
> {
> @@ -1878,20 +1865,6 @@ static void gen_addic_(DisasContext *ctx)
> gen_op_addic(ctx, 1);
> }
>
> -/* addis */
> -static void gen_addis(DisasContext *ctx)
> -{
> - target_long simm = SIMM(ctx->opcode);
> -
> - if (rA(ctx->opcode) == 0) {
> - /* lis case */
> - tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
> - } else {
> - tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
> - cpu_gpr[rA(ctx->opcode)], simm << 16);
> - }
> -}
> -
> /* addpcis */
> static void gen_addpcis(DisasContext *ctx)
> {
> @@ -7903,10 +7876,8 @@ GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
> GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
> GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
> GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
> -GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
> GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
> GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
> -GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
> GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
> GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
> GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
> diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
> index be75085cee..344a3ed54b 100644
> --- a/target/ppc/translate/fixedpoint-impl.c.inc
> +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> @@ -16,3 +16,47 @@
> * You should have received a copy of the GNU Lesser General Public
> * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> */
> +
> +/*
> + * Incorporate CIA into the constant when R=1.
> + * Validate that when R=1, RA=0.
> + */
> +static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
> +{
> + d->rt = a->rt;
> + d->ra = a->ra;
> + d->si = a->si;
> + if (a->r) {
> + if (unlikely(a->ra != 0)) {
> + gen_invalid(ctx);
> + return false;
> + }
> + d->si += ctx->cia;
> + }
> + return true;
> +}
> +
> +static bool trans_ADDI(DisasContext *ctx, arg_D *a)
> +{
> + if (a->ra) {
> + tcg_gen_addi_tl(cpu_gpr[a->rt], cpu_gpr[a->ra], a->si);
> + } else {
> + tcg_gen_movi_tl(cpu_gpr[a->rt], a->si);
> + }
> + return true;
> +}
> +
> +static bool trans_PADDI(DisasContext *ctx, arg_PLS_D *a)
> +{
> + arg_D d;
> + if (!resolve_PLS_D(ctx, &d, a)) {
> + return true;
> + }
> + return trans_ADDI(ctx, &d);
> +}
> +
> +static bool trans_ADDIS(DisasContext *ctx, arg_D *a)
> +{
> + a->si <<= 16;
> + return trans_ADDI(ctx, a);
> +}
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 13/23] target/ppc: Implement PNOP
2021-05-17 20:50 ` [PATCH v5 13/23] target/ppc: Implement PNOP matheus.ferst
@ 2021-05-18 0:36 ` David Gibson
0 siblings, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:36 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 4692 bytes --]
On Mon, May 17, 2021 at 05:50:15PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> The illegal suffix behavior matches what was observed in a
> POWER10 DD2.0 machine.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> v5:
> - Remove argument set from PNOP;
> - Use no_overlap_group for invalid suffixes.
> ---
> target/ppc/insn64.decode | 67 ++++++++++++++++++++++
> target/ppc/translate/fixedpoint-impl.c.inc | 11 ++++
> 2 files changed, 78 insertions(+)
>
> diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
> index 1965088915..9aa5097a98 100644
> --- a/target/ppc/insn64.decode
> +++ b/target/ppc/insn64.decode
> @@ -28,3 +28,70 @@
>
> PADDI 000001 10 0--.-- .................. \
> 001110 ..... ..... ................ @PLS_D
> +
> +### Prefixed No-operation Instruction
> +
> +@PNOP 000001 11 0000-- 000000000000000000 \
> + ................................
> +
> +{
> + [
> + ## Invalid suffixes: Branch instruction
> + # bc[l][a]
> + INVALID ................................ \
> + 010000-------------------------- @PNOP
> + # b[l][a]
> + INVALID ................................ \
> + 010010-------------------------- @PNOP
> + # bclr[l]
> + INVALID ................................ \
> + 010011---------------0000010000- @PNOP
> + # bcctr[l]
> + INVALID ................................ \
> + 010011---------------1000010000- @PNOP
> + # bctar[l]
> + INVALID ................................ \
> + 010011---------------1000110000- @PNOP
> +
> + ## Invalid suffixes: rfebb
> + INVALID ................................ \
> + 010011---------------0010010010- @PNOP
> +
> + ## Invalid suffixes: context synchronizing other than isync
> + # sc
> + INVALID ................................ \
> + 010001------------------------1- @PNOP
> + # scv
> + INVALID ................................ \
> + 010001------------------------01 @PNOP
> + # rfscv
> + INVALID ................................ \
> + 010011---------------0001010010- @PNOP
> + # rfid
> + INVALID ................................ \
> + 010011---------------0000010010- @PNOP
> + # hrfid
> + INVALID ................................ \
> + 010011---------------0100010010- @PNOP
> + # urfid
> + INVALID ................................ \
> + 010011---------------0100110010- @PNOP
> + # stop
> + INVALID ................................ \
> + 010011---------------0101110010- @PNOP
> + # mtmsr w/ L=0
> + INVALID ................................ \
> + 011111---------0-----0010010010- @PNOP
> + # mtmsrd w/ L=0
> + INVALID ................................ \
> + 011111---------0-----0010110010- @PNOP
> +
> + ## Invalid suffixes: Service Processor Attention
> + INVALID ................................ \
> + 000000----------------100000000- @PNOP
> + ]
> +
> + ## Valid suffixes
> + PNOP ................................ \
> + -------------------------------- @PNOP
> +}
> diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
> index 344a3ed54b..ce034a14a7 100644
> --- a/target/ppc/translate/fixedpoint-impl.c.inc
> +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> @@ -60,3 +60,14 @@ static bool trans_ADDIS(DisasContext *ctx, arg_D *a)
> a->si <<= 16;
> return trans_ADDI(ctx, a);
> }
> +
> +static bool trans_INVALID(DisasContext *ctx, arg_INVALID *a)
> +{
> + gen_invalid(ctx);
> + return true;
> +}
> +
> +static bool trans_PNOP(DisasContext *ctx, arg_PNOP *a)
> +{
> + return true;
> +}
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 14/23] TCG: add tcg_constant_tl
2021-05-17 20:50 ` [PATCH v5 14/23] TCG: add tcg_constant_tl matheus.ferst
@ 2021-05-18 0:37 ` David Gibson
0 siblings, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:37 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 1602 bytes --]
On Mon, May 17, 2021 at 05:50:16PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
>
> Used in D/DS/X-form load/store implementation.
>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> include/tcg/tcg-op.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
> index 2cd1faf9c4..ef8a008ea7 100644
> --- a/include/tcg/tcg-op.h
> +++ b/include/tcg/tcg-op.h
> @@ -1096,6 +1096,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
> #define tcg_gen_sextract_tl tcg_gen_sextract_i64
> #define tcg_gen_extract2_tl tcg_gen_extract2_i64
> #define tcg_const_tl tcg_const_i64
> +#define tcg_constant_tl tcg_constant_i64
> #define tcg_const_local_tl tcg_const_local_i64
> #define tcg_gen_movcond_tl tcg_gen_movcond_i64
> #define tcg_gen_add2_tl tcg_gen_add2_i64
> @@ -1209,6 +1210,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
> #define tcg_gen_sextract_tl tcg_gen_sextract_i32
> #define tcg_gen_extract2_tl tcg_gen_extract2_i32
> #define tcg_const_tl tcg_const_i32
> +#define tcg_constant_tl tcg_constant_i32
> #define tcg_const_local_tl tcg_const_local_i32
> #define tcg_gen_movcond_tl tcg_gen_movcond_i32
> #define tcg_gen_add2_tl tcg_gen_add2_i32
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 15/23] target/ppc: Move D/DS/X-form integer loads to decodetree
2021-05-17 20:50 ` [PATCH v5 15/23] target/ppc: Move D/DS/X-form integer loads to decodetree matheus.ferst
@ 2021-05-18 0:44 ` David Gibson
0 siblings, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:44 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 16526 bytes --]
On Mon, May 17, 2021 at 05:50:17PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> These are all connected by macros in the legacy decoding.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/insn32.decode | 37 ++++++
> target/ppc/translate.c | 147 ++++-----------------
> target/ppc/translate/fixedpoint-impl.c.inc | 89 +++++++++++++
> 3 files changed, 150 insertions(+), 123 deletions(-)
>
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index e7c062d8b4..70f64c235b 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -20,6 +20,43 @@
> &D rt ra si:int64_t
> @D ...... rt:5 ra:5 si:s16 &D
>
> +%ds_si 2:s14 !function=times_4
> +@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
> +
> +&X rt ra rb
> +@X ...... rt:5 ra:5 rb:5 .......... . &X
> +
> +### Fixed-Point Load Instructions
> +
> +LBZ 100010 ..... ..... ................ @D
> +LBZU 100011 ..... ..... ................ @D
> +LBZX 011111 ..... ..... ..... 0001010111 - @X
> +LBZUX 011111 ..... ..... ..... 0001110111 - @X
> +
> +LHZ 101000 ..... ..... ................ @D
> +LHZU 101001 ..... ..... ................ @D
> +LHZX 011111 ..... ..... ..... 0100010111 - @X
> +LHZUX 011111 ..... ..... ..... 0100110111 - @X
> +
> +LHA 101010 ..... ..... ................ @D
> +LHAU 101011 ..... ..... ................ @D
> +LHAX 011111 ..... ..... ..... 0101010111 - @X
> +LHAXU 011111 ..... ..... ..... 0101110111 - @X
> +
> +LWZ 100000 ..... ..... ................ @D
> +LWZU 100001 ..... ..... ................ @D
> +LWZX 011111 ..... ..... ..... 0000010111 - @X
> +LWZUX 011111 ..... ..... ..... 0000110111 - @X
> +
> +LWA 111010 ..... ..... ..............10 @DS
> +LWAX 011111 ..... ..... ..... 0101010101 - @X
> +LWAUX 011111 ..... ..... ..... 0101110101 - @X
> +
> +LD 111010 ..... ..... ..............00 @DS
> +LDU 111010 ..... ..... ..............01 @DS
> +LDX 011111 ..... ..... ..... 0000010101 - @X
> +LDUX 011111 ..... ..... ..... 0000110101 - @X
> +
> ### Fixed-Point Arithmetic Instructions
>
> ADDI 001110 ..... ..... ................ @D
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 5bf9001141..e037efcfe1 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -3409,54 +3409,6 @@ GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
> GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
> #endif
>
> -#define GEN_LD(name, ldop, opc, type) \
> -static void glue(gen_, name)(DisasContext *ctx) \
> -{ \
> - TCGv EA; \
> - gen_set_access_type(ctx, ACCESS_INT); \
> - EA = tcg_temp_new(); \
> - gen_addr_imm_index(ctx, EA, 0); \
> - gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
> - tcg_temp_free(EA); \
> -}
> -
> -#define GEN_LDU(name, ldop, opc, type) \
> -static void glue(gen_, name##u)(DisasContext *ctx) \
> -{ \
> - TCGv EA; \
> - if (unlikely(rA(ctx->opcode) == 0 || \
> - rA(ctx->opcode) == rD(ctx->opcode))) { \
> - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
> - return; \
> - } \
> - gen_set_access_type(ctx, ACCESS_INT); \
> - EA = tcg_temp_new(); \
> - if (type == PPC_64B) \
> - gen_addr_imm_index(ctx, EA, 0x03); \
> - else \
> - gen_addr_imm_index(ctx, EA, 0); \
> - gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
> - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
> - tcg_temp_free(EA); \
> -}
> -
> -#define GEN_LDUX(name, ldop, opc2, opc3, type) \
> -static void glue(gen_, name##ux)(DisasContext *ctx) \
> -{ \
> - TCGv EA; \
> - if (unlikely(rA(ctx->opcode) == 0 || \
> - rA(ctx->opcode) == rD(ctx->opcode))) { \
> - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
> - return; \
> - } \
> - gen_set_access_type(ctx, ACCESS_INT); \
> - EA = tcg_temp_new(); \
> - gen_addr_reg_index(ctx, EA); \
> - gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
> - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
> - tcg_temp_free(EA); \
> -}
> -
> #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
> static void glue(gen_, name##x)(DisasContext *ctx) \
> { \
> @@ -3475,21 +3427,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) \
> #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
> GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
>
> -#define GEN_LDS(name, ldop, op, type) \
> -GEN_LD(name, ldop, op | 0x20, type); \
> -GEN_LDU(name, ldop, op | 0x21, type); \
> -GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
> -GEN_LDX(name, ldop, 0x17, op | 0x00, type)
> -
> -/* lbz lbzu lbzux lbzx */
> -GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
> -/* lha lhau lhaux lhax */
> -GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
> -/* lhz lhzu lhzux lhzx */
> -GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
> -/* lwz lwzu lwzux lwzx */
> -GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
> -
> #define GEN_LDEPX(name, ldop, opc2, opc3) \
> static void glue(gen_, name##epx)(DisasContext *ctx) \
> { \
> @@ -3510,47 +3447,12 @@ GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
> #endif
>
> #if defined(TARGET_PPC64)
> -/* lwaux */
> -GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
> -/* lwax */
> -GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
> -/* ldux */
> -GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
> -/* ldx */
> -GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
> -
> /* CI load/store variants */
> GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
> GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
> GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
> GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
>
> -static void gen_ld(DisasContext *ctx)
> -{
> - TCGv EA;
> - if (Rc(ctx->opcode)) {
> - if (unlikely(rA(ctx->opcode) == 0 ||
> - rA(ctx->opcode) == rD(ctx->opcode))) {
> - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
> - return;
> - }
> - }
> - gen_set_access_type(ctx, ACCESS_INT);
> - EA = tcg_temp_new();
> - gen_addr_imm_index(ctx, EA, 0x03);
> - if (ctx->opcode & 0x02) {
> - /* lwa (lwau is undefined) */
> - gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
> - } else {
> - /* ld - ldu */
> - gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
> - }
> - if (Rc(ctx->opcode)) {
> - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
> - }
> - tcg_temp_free(EA);
> -}
> -
> /* lq */
> static void gen_lq(DisasContext *ctx)
> {
> @@ -7723,6 +7625,14 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high)
> tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
> }
>
> +/*
> + * Helpers for decodetree used by !function for decoding arguments.
> + */
> +static int times_4(DisasContext *ctx, int x)
> +{
> + return x * 4;
> +}
> +
> /*
> * Helpers for trans_* functions to check for specific insns flags.
> * Use token pasting to ensure that we use the proper flag with the
> @@ -7749,6 +7659,21 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high)
> # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B)
> #endif
>
> +/*
> + * Helpers for implementing sets of trans_* functions.
> + * Defer the implementation of NAME to FUNC, with optional extra arguments.
> + */
> +#define TRANS(NAME, FUNC, ...) \
> + static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
> + { return FUNC(ctx, a, __VA_ARGS__); }
> +
> +#define TRANS64(NAME, FUNC, ...) \
> + static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
> + { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); }
> +
> +/* TODO: More TRANS* helpers for extra insn_flags checks. */
> +
> +
> #include "decode-insn32.c.inc"
> #include "decode-insn64.c.inc"
> #include "translate/fixedpoint-impl.c.inc"
> @@ -7933,7 +7858,6 @@ GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
> PPC_NONE, PPC2_ISA300),
> #endif
> #if defined(TARGET_PPC64)
> -GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
> GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
> GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
> #endif
> @@ -8299,34 +8223,11 @@ GEN_PPC64_R2(rldcr, 0x1E, 0x09),
> GEN_PPC64_R4(rldimi, 0x1E, 0x06),
> #endif
>
> -#undef GEN_LD
> -#undef GEN_LDU
> -#undef GEN_LDUX
> #undef GEN_LDX_E
> -#undef GEN_LDS
> -#define GEN_LD(name, ldop, opc, type) \
> -GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
> -#define GEN_LDU(name, ldop, opc, type) \
> -GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
> -#define GEN_LDUX(name, ldop, opc2, opc3, type) \
> -GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
> #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
> GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
> -#define GEN_LDS(name, ldop, op, type) \
> -GEN_LD(name, ldop, op | 0x20, type) \
> -GEN_LDU(name, ldop, op | 0x21, type) \
> -GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
> -GEN_LDX(name, ldop, 0x17, op | 0x00, type)
> -
> -GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
> -GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
> -GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
> -GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
> +
> #if defined(TARGET_PPC64)
> -GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
> -GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
> -GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
> -GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
> GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
>
> /* HV/P7 and later only */
> diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
> index ce034a14a7..6140dd41ca 100644
> --- a/target/ppc/translate/fixedpoint-impl.c.inc
> +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> @@ -36,6 +36,95 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
> return true;
> }
>
> +/*
> + * Fixed-Point Load/Store Instructions
> + */
> +
> +static bool do_ldst(DisasContext *ctx, int rt, int ra, TCGv displ, bool update,
> + bool store, MemOp mop)
> +{
> + TCGv ea;
> +
> + if (update && (ra == 0 || (!store && ra == rt))) {
> + gen_invalid(ctx);
> + return true;
> + }
> + gen_set_access_type(ctx, ACCESS_INT);
> +
> + ea = tcg_temp_new();
> + if (ra) {
> + tcg_gen_add_tl(ea, cpu_gpr[ra], displ);
> + } else {
> + tcg_gen_mov_tl(ea, displ);
> + }
> + if (NARROW_MODE(ctx)) {
> + tcg_gen_ext32u_tl(ea, ea);
> + }
> + mop ^= ctx->default_tcg_memop_mask;
> + if (store) {
> + tcg_gen_qemu_st_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
> + } else {
> + tcg_gen_qemu_ld_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
> + }
> + if (update) {
> + tcg_gen_mov_tl(cpu_gpr[ra], ea);
> + }
> + tcg_temp_free(ea);
> +
> + return true;
> +}
> +
> +static bool do_ldst_D(DisasContext *ctx, arg_D *a, bool update, bool store,
> + MemOp mop)
> +{
> + return do_ldst(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store, mop);
> +}
> +
> +static bool do_ldst_X(DisasContext *ctx, arg_X *a, bool update,
> + bool store, MemOp mop)
> +{
> + return do_ldst(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, mop);
> +}
> +
> +/* Load Byte and Zero */
> +TRANS(LBZ, do_ldst_D, false, false, MO_UB)
> +TRANS(LBZX, do_ldst_X, false, false, MO_UB)
> +TRANS(LBZU, do_ldst_D, true, false, MO_UB)
> +TRANS(LBZUX, do_ldst_X, true, false, MO_UB)
> +
> +/* Load Halfword and Zero */
> +TRANS(LHZ, do_ldst_D, false, false, MO_UW)
> +TRANS(LHZX, do_ldst_X, false, false, MO_UW)
> +TRANS(LHZU, do_ldst_D, true, false, MO_UW)
> +TRANS(LHZUX, do_ldst_X, true, false, MO_UW)
> +
> +/* Load Halfword Algebraic */
> +TRANS(LHA, do_ldst_D, false, false, MO_SW)
> +TRANS(LHAX, do_ldst_X, false, false, MO_SW)
> +TRANS(LHAU, do_ldst_D, true, false, MO_SW)
> +TRANS(LHAXU, do_ldst_X, true, false, MO_SW)
> +
> +/* Load Word and Zero */
> +TRANS(LWZ, do_ldst_D, false, false, MO_UL)
> +TRANS(LWZX, do_ldst_X, false, false, MO_UL)
> +TRANS(LWZU, do_ldst_D, true, false, MO_UL)
> +TRANS(LWZUX, do_ldst_X, true, false, MO_UL)
> +
> +/* Load Word Algebraic */
> +TRANS64(LWA, do_ldst_D, false, false, MO_SL)
> +TRANS64(LWAX, do_ldst_X, false, false, MO_SL)
> +TRANS64(LWAUX, do_ldst_X, true, false, MO_SL)
> +
> +/* Load Doubleword */
> +TRANS64(LD, do_ldst_D, false, false, MO_Q)
> +TRANS64(LDX, do_ldst_X, false, false, MO_Q)
> +TRANS64(LDU, do_ldst_D, true, false, MO_Q)
> +TRANS64(LDUX, do_ldst_X, true, false, MO_Q)
> +
> +/*
> + * Fixed-Point Arithmetic Instructions
> + */
> +
> static bool trans_ADDI(DisasContext *ctx, arg_D *a)
> {
> if (a->ra) {
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 16/23] target/ppc: Implement prefixed integer load instructions
2021-05-17 20:50 ` [PATCH v5 16/23] target/ppc: Implement prefixed integer load instructions matheus.ferst
@ 2021-05-18 0:45 ` David Gibson
0 siblings, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:45 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 4429 bytes --]
On Mon, May 17, 2021 at 05:50:18PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/insn64.decode | 15 +++++++++++++++
> target/ppc/translate/fixedpoint-impl.c.inc | 16 ++++++++++++++++
> 2 files changed, 31 insertions(+)
>
> diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
> index 9aa5097a98..547bd1736f 100644
> --- a/target/ppc/insn64.decode
> +++ b/target/ppc/insn64.decode
> @@ -24,6 +24,21 @@
> ...... rt:5 ra:5 ................ \
> &PLS_D si=%pls_si
>
> +### Fixed-Point Load Instructions
> +
> +PLBZ 000001 10 0--.-- .................. \
> + 100010 ..... ..... ................ @PLS_D
> +PLHZ 000001 10 0--.-- .................. \
> + 101000 ..... ..... ................ @PLS_D
> +PLHA 000001 10 0--.-- .................. \
> + 101010 ..... ..... ................ @PLS_D
> +PLWZ 000001 10 0--.-- .................. \
> + 100000 ..... ..... ................ @PLS_D
> +PLWA 000001 00 0--.-- .................. \
> + 101001 ..... ..... ................ @PLS_D
> +PLD 000001 00 0--.-- .................. \
> + 111001 ..... ..... ................ @PLS_D
> +
> ### Fixed-Point Arithmetic Instructions
>
> PADDI 000001 10 0--.-- .................. \
> diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
> index 6140dd41ca..7687f31d6f 100644
> --- a/target/ppc/translate/fixedpoint-impl.c.inc
> +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> @@ -80,6 +80,16 @@ static bool do_ldst_D(DisasContext *ctx, arg_D *a, bool update, bool store,
> return do_ldst(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store, mop);
> }
>
> +static bool do_ldst_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool update,
> + bool store, MemOp mop)
> +{
> + arg_D d;
> + if (!resolve_PLS_D(ctx, &d, a)) {
> + return true;
> + }
> + return do_ldst_D(ctx, &d, update, store, mop);
> +}
> +
> static bool do_ldst_X(DisasContext *ctx, arg_X *a, bool update,
> bool store, MemOp mop)
> {
> @@ -91,35 +101,41 @@ TRANS(LBZ, do_ldst_D, false, false, MO_UB)
> TRANS(LBZX, do_ldst_X, false, false, MO_UB)
> TRANS(LBZU, do_ldst_D, true, false, MO_UB)
> TRANS(LBZUX, do_ldst_X, true, false, MO_UB)
> +TRANS(PLBZ, do_ldst_PLS_D, false, false, MO_UB)
>
> /* Load Halfword and Zero */
> TRANS(LHZ, do_ldst_D, false, false, MO_UW)
> TRANS(LHZX, do_ldst_X, false, false, MO_UW)
> TRANS(LHZU, do_ldst_D, true, false, MO_UW)
> TRANS(LHZUX, do_ldst_X, true, false, MO_UW)
> +TRANS(PLHZ, do_ldst_PLS_D, false, false, MO_UW)
>
> /* Load Halfword Algebraic */
> TRANS(LHA, do_ldst_D, false, false, MO_SW)
> TRANS(LHAX, do_ldst_X, false, false, MO_SW)
> TRANS(LHAU, do_ldst_D, true, false, MO_SW)
> TRANS(LHAXU, do_ldst_X, true, false, MO_SW)
> +TRANS(PLHA, do_ldst_PLS_D, false, false, MO_SW)
>
> /* Load Word and Zero */
> TRANS(LWZ, do_ldst_D, false, false, MO_UL)
> TRANS(LWZX, do_ldst_X, false, false, MO_UL)
> TRANS(LWZU, do_ldst_D, true, false, MO_UL)
> TRANS(LWZUX, do_ldst_X, true, false, MO_UL)
> +TRANS(PLWZ, do_ldst_PLS_D, false, false, MO_UL)
>
> /* Load Word Algebraic */
> TRANS64(LWA, do_ldst_D, false, false, MO_SL)
> TRANS64(LWAX, do_ldst_X, false, false, MO_SL)
> TRANS64(LWAUX, do_ldst_X, true, false, MO_SL)
> +TRANS64(PLWA, do_ldst_PLS_D, false, false, MO_SL)
>
> /* Load Doubleword */
> TRANS64(LD, do_ldst_D, false, false, MO_Q)
> TRANS64(LDX, do_ldst_X, false, false, MO_Q)
> TRANS64(LDU, do_ldst_D, true, false, MO_Q)
> TRANS64(LDUX, do_ldst_X, true, false, MO_Q)
> +TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q)
>
> /*
> * Fixed-Point Arithmetic Instructions
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 17/23] target/ppc: Move D/DS/X-form integer stores to decodetree
2021-05-17 20:50 ` [PATCH v5 17/23] target/ppc: Move D/DS/X-form integer stores to decodetree matheus.ferst
@ 2021-05-18 0:47 ` David Gibson
0 siblings, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:47 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 11284 bytes --]
On Mon, May 17, 2021 at 05:50:19PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> These are all connected by macros in the legacy decoding.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/insn32.decode | 22 ++++++
> target/ppc/translate.c | 85 +---------------------
> target/ppc/translate/fixedpoint-impl.c.inc | 24 ++++++
> 3 files changed, 49 insertions(+), 82 deletions(-)
>
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index 70f64c235b..00ec0f4328 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -57,6 +57,28 @@ LDU 111010 ..... ..... ..............01 @DS
> LDX 011111 ..... ..... ..... 0000010101 - @X
> LDUX 011111 ..... ..... ..... 0000110101 - @X
>
> +### Fixed-Point Store Instructions
> +
> +STB 100110 ..... ..... ................ @D
> +STBU 100111 ..... ..... ................ @D
> +STBX 011111 ..... ..... ..... 0011010111 - @X
> +STBUX 011111 ..... ..... ..... 0011110111 - @X
> +
> +STH 101100 ..... ..... ................ @D
> +STHU 101101 ..... ..... ................ @D
> +STHX 011111 ..... ..... ..... 0110010111 - @X
> +STHUX 011111 ..... ..... ..... 0110110111 - @X
> +
> +STW 100100 ..... ..... ................ @D
> +STWU 100101 ..... ..... ................ @D
> +STWX 011111 ..... ..... ..... 0010010111 - @X
> +STWUX 011111 ..... ..... ..... 0010110111 - @X
> +
> +STD 111110 ..... ..... ..............00 @DS
> +STDU 111110 ..... ..... ..............01 @DS
> +STDX 011111 ..... ..... ..... 0010010101 - @X
> +STDUX 011111 ..... ..... ..... 0010110101 - @X
> +
> ### Fixed-Point Arithmetic Instructions
>
> ADDI 001110 ..... ..... ................ @D
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index e037efcfe1..bf624edba6 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -3385,7 +3385,9 @@ static void glue(gen_qemu_, stop)(DisasContext *ctx, \
> tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
> }
>
> +#if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY)
> GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
> +#endif
> GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
> GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
>
> @@ -3518,52 +3520,6 @@ static void gen_lq(DisasContext *ctx)
> #endif
>
> /*** Integer store ***/
> -#define GEN_ST(name, stop, opc, type) \
> -static void glue(gen_, name)(DisasContext *ctx) \
> -{ \
> - TCGv EA; \
> - gen_set_access_type(ctx, ACCESS_INT); \
> - EA = tcg_temp_new(); \
> - gen_addr_imm_index(ctx, EA, 0); \
> - gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
> - tcg_temp_free(EA); \
> -}
> -
> -#define GEN_STU(name, stop, opc, type) \
> -static void glue(gen_, stop##u)(DisasContext *ctx) \
> -{ \
> - TCGv EA; \
> - if (unlikely(rA(ctx->opcode) == 0)) { \
> - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
> - return; \
> - } \
> - gen_set_access_type(ctx, ACCESS_INT); \
> - EA = tcg_temp_new(); \
> - if (type == PPC_64B) \
> - gen_addr_imm_index(ctx, EA, 0x03); \
> - else \
> - gen_addr_imm_index(ctx, EA, 0); \
> - gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
> - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
> - tcg_temp_free(EA); \
> -}
> -
> -#define GEN_STUX(name, stop, opc2, opc3, type) \
> -static void glue(gen_, name##ux)(DisasContext *ctx) \
> -{ \
> - TCGv EA; \
> - if (unlikely(rA(ctx->opcode) == 0)) { \
> - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
> - return; \
> - } \
> - gen_set_access_type(ctx, ACCESS_INT); \
> - EA = tcg_temp_new(); \
> - gen_addr_reg_index(ctx, EA); \
> - gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
> - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
> - tcg_temp_free(EA); \
> -}
> -
> #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
> static void glue(gen_, name##x)(DisasContext *ctx) \
> { \
> @@ -3581,19 +3537,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) \
> #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
> GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
>
> -#define GEN_STS(name, stop, op, type) \
> -GEN_ST(name, stop, op | 0x20, type); \
> -GEN_STU(name, stop, op | 0x21, type); \
> -GEN_STUX(name, stop, 0x17, op | 0x01, type); \
> -GEN_STX(name, stop, 0x17, op | 0x00, type)
> -
> -/* stb stbu stbux stbx */
> -GEN_STS(stb, st8, 0x06, PPC_INTEGER);
> -/* sth sthu sthux sthx */
> -GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
> -/* stw stwu stwux stwx */
> -GEN_STS(stw, st32, 0x04, PPC_INTEGER);
> -
> #define GEN_STEPX(name, stop, opc2, opc3) \
> static void glue(gen_, name##epx)(DisasContext *ctx) \
> { \
> @@ -3615,8 +3558,6 @@ GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04)
> #endif
>
> #if defined(TARGET_PPC64)
> -GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
> -GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
> GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
> GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
> GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
> @@ -8252,31 +8193,11 @@ GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
> GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
> #endif
>
> -#undef GEN_ST
> -#undef GEN_STU
> -#undef GEN_STUX
> #undef GEN_STX_E
> -#undef GEN_STS
> -#define GEN_ST(name, stop, opc, type) \
> -GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
> -#define GEN_STU(name, stop, opc, type) \
> -GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
> -#define GEN_STUX(name, stop, opc2, opc3, type) \
> -GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
> #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
> GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
> -#define GEN_STS(name, stop, op, type) \
> -GEN_ST(name, stop, op | 0x20, type) \
> -GEN_STU(name, stop, op | 0x21, type) \
> -GEN_STUX(name, stop, 0x17, op | 0x01, type) \
> -GEN_STX(name, stop, 0x17, op | 0x00, type)
> -
> -GEN_STS(stb, st8, 0x06, PPC_INTEGER)
> -GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
> -GEN_STS(stw, st32, 0x04, PPC_INTEGER)
> +
> #if defined(TARGET_PPC64)
> -GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
> -GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
> GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
> GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
> GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
> diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
> index 7687f31d6f..adeee33289 100644
> --- a/target/ppc/translate/fixedpoint-impl.c.inc
> +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> @@ -137,6 +137,30 @@ TRANS64(LDU, do_ldst_D, true, false, MO_Q)
> TRANS64(LDUX, do_ldst_X, true, false, MO_Q)
> TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q)
>
> +/* Store Byte */
> +TRANS(STB, do_ldst_D, false, true, MO_UB)
> +TRANS(STBX, do_ldst_X, false, true, MO_UB)
> +TRANS(STBU, do_ldst_D, true, true, MO_UB)
> +TRANS(STBUX, do_ldst_X, true, true, MO_UB)
> +
> +/* Store Halfword */
> +TRANS(STH, do_ldst_D, false, true, MO_UW)
> +TRANS(STHX, do_ldst_X, false, true, MO_UW)
> +TRANS(STHU, do_ldst_D, true, true, MO_UW)
> +TRANS(STHUX, do_ldst_X, true, true, MO_UW)
> +
> +/* Store Word */
> +TRANS(STW, do_ldst_D, false, true, MO_UL)
> +TRANS(STWX, do_ldst_X, false, true, MO_UL)
> +TRANS(STWU, do_ldst_D, true, true, MO_UL)
> +TRANS(STWUX, do_ldst_X, true, true, MO_UL)
> +
> +/* Store Doubleword */
> +TRANS64(STD, do_ldst_D, false, true, MO_Q)
> +TRANS64(STDX, do_ldst_X, false, true, MO_Q)
> +TRANS64(STDU, do_ldst_D, true, true, MO_Q)
> +TRANS64(STDUX, do_ldst_X, true, true, MO_Q)
> +
> /*
> * Fixed-Point Arithmetic Instructions
> */
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 18/23] target/ppc: Implement prefixed integer store instructions
2021-05-17 20:50 ` [PATCH v5 18/23] target/ppc: Implement prefixed integer store instructions matheus.ferst
@ 2021-05-18 0:47 ` David Gibson
0 siblings, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:47 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 3087 bytes --]
On Mon, May 17, 2021 at 05:50:20PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/insn64.decode | 12 ++++++++++++
> target/ppc/translate/fixedpoint-impl.c.inc | 4 ++++
> 2 files changed, 16 insertions(+)
>
> diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
> index 547bd1736f..72c5944a53 100644
> --- a/target/ppc/insn64.decode
> +++ b/target/ppc/insn64.decode
> @@ -39,6 +39,18 @@ PLWA 000001 00 0--.-- .................. \
> PLD 000001 00 0--.-- .................. \
> 111001 ..... ..... ................ @PLS_D
>
> +### Fixed-Point Store Instructions
> +
> +PSTW 000001 10 0--.-- .................. \
> + 100100 ..... ..... ................ @PLS_D
> +PSTB 000001 10 0--.-- .................. \
> + 100110 ..... ..... ................ @PLS_D
> +PSTH 000001 10 0--.-- .................. \
> + 101100 ..... ..... ................ @PLS_D
> +
> +PSTD 000001 00 0--.-- .................. \
> + 111101 ..... ..... ................ @PLS_D
> +
> ### Fixed-Point Arithmetic Instructions
>
> PADDI 000001 10 0--.-- .................. \
> diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
> index adeee33289..2d2d874146 100644
> --- a/target/ppc/translate/fixedpoint-impl.c.inc
> +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> @@ -142,24 +142,28 @@ TRANS(STB, do_ldst_D, false, true, MO_UB)
> TRANS(STBX, do_ldst_X, false, true, MO_UB)
> TRANS(STBU, do_ldst_D, true, true, MO_UB)
> TRANS(STBUX, do_ldst_X, true, true, MO_UB)
> +TRANS(PSTB, do_ldst_PLS_D, false, true, MO_UB)
>
> /* Store Halfword */
> TRANS(STH, do_ldst_D, false, true, MO_UW)
> TRANS(STHX, do_ldst_X, false, true, MO_UW)
> TRANS(STHU, do_ldst_D, true, true, MO_UW)
> TRANS(STHUX, do_ldst_X, true, true, MO_UW)
> +TRANS(PSTH, do_ldst_PLS_D, false, true, MO_UW)
>
> /* Store Word */
> TRANS(STW, do_ldst_D, false, true, MO_UL)
> TRANS(STWX, do_ldst_X, false, true, MO_UL)
> TRANS(STWU, do_ldst_D, true, true, MO_UL)
> TRANS(STWUX, do_ldst_X, true, true, MO_UL)
> +TRANS(PSTW, do_ldst_PLS_D, false, true, MO_UL)
>
> /* Store Doubleword */
> TRANS64(STD, do_ldst_D, false, true, MO_Q)
> TRANS64(STDX, do_ldst_X, false, true, MO_Q)
> TRANS64(STDU, do_ldst_D, true, true, MO_Q)
> TRANS64(STDUX, do_ldst_X, true, true, MO_Q)
> +TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_Q)
>
> /*
> * Fixed-Point Arithmetic Instructions
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 19/23] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions
2021-05-17 20:50 ` [PATCH v5 19/23] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions matheus.ferst
@ 2021-05-18 0:49 ` David Gibson
2021-05-18 9:48 ` Richard Henderson
1 sibling, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:49 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 3123 bytes --]
On Mon, May 17, 2021 at 05:50:21PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
>
> Implements the following PowerISA v3.1 instructions:
> setbc: Set Boolean Condition
> setbcr: Set Boolean Condition Reverse
> setnbc: Set Negative Boolean Condition
> setnbcr: Set Negative Boolean Condition Reverse
>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> v5:
> - Style fix;
> - Use tcg_gen_setcondi_tl instead of tcg_gen_movcond_tl.
> ---
> target/ppc/insn32.decode | 10 ++++++++++
> target/ppc/translate/fixedpoint-impl.c.inc | 23 ++++++++++++++++++++++
> 2 files changed, 33 insertions(+)
>
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index 00ec0f4328..bc69c70493 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -26,6 +26,9 @@
> &X rt ra rb
> @X ...... rt:5 ra:5 rb:5 .......... . &X
>
> +&X_bi rt bi
> +@X_bi ...... rt:5 bi:5 ----- .......... - &X_bi
> +
> ### Fixed-Point Load Instructions
>
> LBZ 100010 ..... ..... ................ @D
> @@ -83,3 +86,10 @@ STDUX 011111 ..... ..... ..... 0010110101 - @X
>
> ADDI 001110 ..... ..... ................ @D
> ADDIS 001111 ..... ..... ................ @D
> +
> +### Move To/From System Register Instructions
> +
> +SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
> +SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
> +SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
> +SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
> diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
> index 2d2d874146..204848d017 100644
> --- a/target/ppc/translate/fixedpoint-impl.c.inc
> +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> @@ -204,3 +204,26 @@ static bool trans_PNOP(DisasContext *ctx, arg_PNOP *a)
> {
> return true;
> }
> +
> +static bool do_set_bool_cond(DisasContext *ctx, arg_X_bi *a, bool neg, bool rev)
> +{
> + REQUIRE_INSNS_FLAGS2(ctx, ISA310);
> + uint32_t mask = 0x08 >> (a->bi & 0x03);
> + TCGCond cond = rev ? TCG_COND_EQ : TCG_COND_NE;
> + TCGv temp = tcg_temp_new();
> +
> + tcg_gen_extu_i32_tl(temp, cpu_crf[a->bi >> 2]);
> + tcg_gen_andi_tl(temp, temp, mask);
> + tcg_gen_setcondi_tl(cond, cpu_gpr[a->rt], temp, 0);
> + if(neg) {
> + tcg_gen_neg_tl(cpu_gpr[a->rt], cpu_gpr[a->rt]);
> + }
> + tcg_temp_free(temp);
> +
> + return true;
> +}
> +
> +TRANS(SETBC, do_set_bool_cond, false, false)
> +TRANS(SETBCR, do_set_bool_cond, false, true)
> +TRANS(SETNBC, do_set_bool_cond, true, false)
> +TRANS(SETNBCR, do_set_bool_cond, true, true)
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 20/23] target/ppc: Implement cfuged instruction
2021-05-17 20:50 ` [PATCH v5 20/23] target/ppc: Implement cfuged instruction matheus.ferst
@ 2021-05-18 0:51 ` David Gibson
0 siblings, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:51 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 5334 bytes --]
On Mon, May 17, 2021 at 05:50:22PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> v5:
> - Comments to explain helper_cfuged implementation.
> ---
> target/ppc/helper.h | 1 +
> target/ppc/insn32.decode | 4 ++
> target/ppc/int_helper.c | 62 ++++++++++++++++++++++
> target/ppc/translate/fixedpoint-impl.c.inc | 12 +++++
> 4 files changed, 79 insertions(+)
>
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index ea9f2a236c..c517b9f025 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -46,6 +46,7 @@ DEF_HELPER_4(divwe, tl, env, tl, tl, i32)
> DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
> DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
> DEF_HELPER_3(sraw, tl, env, tl, tl)
> +DEF_HELPER_FLAGS_2(cfuged, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> #if defined(TARGET_PPC64)
> DEF_HELPER_FLAGS_2(cmpeqb, TCG_CALL_NO_RWG_SE, i32, tl, tl)
> DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index bc69c70493..d4044d9069 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -87,6 +87,10 @@ STDUX 011111 ..... ..... ..... 0010110101 - @X
> ADDI 001110 ..... ..... ................ @D
> ADDIS 001111 ..... ..... ................ @D
>
> +## Fixed-Point Logical Instructions
> +
> +CFUGED 011111 ..... ..... ..... 0011011100 - @X
> +
> ### Move To/From System Register Instructions
>
> SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
> diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
> index 41f8477d4b..efa833ef64 100644
> --- a/target/ppc/int_helper.c
> +++ b/target/ppc/int_helper.c
> @@ -320,6 +320,68 @@ target_ulong helper_popcntb(target_ulong val)
> }
> #endif
>
> +uint64_t helper_cfuged(uint64_t src, uint64_t mask)
> +{
> + /*
> + * Instead of processing the mask bit-by-bit from the most significant to
> + * the least significant bit, as described in PowerISA, we'll handle it in
> + * blocks of 'n' zeros/ones from LSB to MSB. To avoid the decision to use
> + * ctz or cto, we negate the mask at the end of the loop.
> + */
> + target_ulong m, left = 0, right = 0;
> + unsigned int n, i = 64;
> + bool bit = false; /* tracks if we are processing zeros or ones */
> +
> + if (mask == 0 || mask == -1) {
> + return src;
> + }
> +
> + /* Processes the mask in blocks, from LSB to MSB */
> + while (i) {
> + /* Find how many bits we should take */
> + n = ctz64(mask);
> + if (n > i) {
> + n = i;
> + }
> +
> + /*
> + * Extracts 'n' trailing bits of src and put them on the leading 'n'
> + * bits of 'right' or 'left', pushing down the previously extracted
> + * values.
> + */
> + m = (1ll << n) - 1;
> + if (bit) {
> + right = ror64(right | (src & m), n);
> + } else {
> + left = ror64(left | (src & m), n);
> + }
> +
> + /*
> + * Discards the processed bits from 'src' and 'mask'. Note that we are
> + * removing 'n' trailing zeros from 'mask', but the logical shift will
> + * add 'n' leading zeros back, so the population count of 'mask' is kept
> + * the same.
> + */
> + src >>= n;
> + mask >>= n;
> + i -= n;
> + bit = !bit;
> + mask = ~mask;
> + }
> +
> + /*
> + * At the end, right was ror'ed ctpop(mask) times. To put it back in place,
> + * we'll shift it more 64-ctpop(mask) times.
> + */
> + if (bit) {
> + n = ctpop64(mask);
> + } else {
> + n = 64 - ctpop64(mask);
> + }
> +
> + return left | (right >> n);
> +}
> +
> /*****************************************************************************/
> /* PowerPC 601 specific instructions (POWER bridge) */
> target_ulong helper_div(CPUPPCState *env, target_ulong arg1, target_ulong arg2)
> diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
> index 204848d017..4038143efb 100644
> --- a/target/ppc/translate/fixedpoint-impl.c.inc
> +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> @@ -227,3 +227,15 @@ TRANS(SETBC, do_set_bool_cond, false, false)
> TRANS(SETBCR, do_set_bool_cond, false, true)
> TRANS(SETNBC, do_set_bool_cond, true, false)
> TRANS(SETNBCR, do_set_bool_cond, true, true)
> +
> +static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_INSNS_FLAGS2(ctx, ISA310);
> +#if defined(TARGET_PPC64)
> + gen_helper_cfuged(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
> +#else
> + qemu_build_not_reached();
> +#endif
> + return true;
> +}
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 21/23] target/ppc: Implement vcfuged instruction
2021-05-17 20:50 ` [PATCH v5 21/23] target/ppc: Implement vcfuged instruction matheus.ferst
@ 2021-05-18 0:52 ` David Gibson
2021-05-18 9:54 ` Richard Henderson
1 sibling, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:52 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 4457 bytes --]
On Mon, May 17, 2021 at 05:50:23PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> v5:
> - New REQUIRE_ALTIVEC macro;
> - REQUIRE_INSNS_FLAGS2.
> ---
> target/ppc/insn32.decode | 7 ++++
> target/ppc/translate.c | 1 +
> target/ppc/translate/vector-impl.c.inc | 56 ++++++++++++++++++++++++++
> 3 files changed, 64 insertions(+)
> create mode 100644 target/ppc/translate/vector-impl.c.inc
>
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index d4044d9069..77edf407ab 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -23,6 +23,9 @@
> %ds_si 2:s14 !function=times_4
> @DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
>
> +&VX vrt vra vrb
> +@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
> +
> &X rt ra rb
> @X ...... rt:5 ra:5 rb:5 .......... . &X
>
> @@ -97,3 +100,7 @@ SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
> SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
> SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
> SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
> +
> +## Vector Bit Manipulation Instruction
> +
> +VCFUGED 000100 ..... ..... ..... 10101001101 @VX
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index bf624edba6..f56ed5866e 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -7624,6 +7624,7 @@ static int times_4(DisasContext *ctx, int x)
> #include "translate/vmx-impl.c.inc"
>
> #include "translate/vsx-impl.c.inc"
> +#include "translate/vector-impl.c.inc"
>
> #include "translate/dfp-impl.c.inc"
>
> diff --git a/target/ppc/translate/vector-impl.c.inc b/target/ppc/translate/vector-impl.c.inc
> new file mode 100644
> index 0000000000..4f986cf53f
> --- /dev/null
> +++ b/target/ppc/translate/vector-impl.c.inc
> @@ -0,0 +1,56 @@
> +/*
> + * Power ISA decode for Vector Facility instructions
> + *
> + * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#define REQUIRE_ALTIVEC(CTX) \
> + do { \
> + if (unlikely(!(CTX)->altivec_enabled)) { \
> + gen_exception((CTX), POWERPC_EXCP_VPU); \
> + return true; \
> + } \
> + } while (0)
> +
> +static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
> +{
> + TCGv_i64 tgt, src, mask;
> +
> + REQUIRE_INSNS_FLAGS2(ctx, ISA310);
> + REQUIRE_ALTIVEC(ctx);
> +
> + tgt = tcg_temp_new_i64();
> + src = tcg_temp_new_i64();
> + mask = tcg_temp_new_i64();
> +
> + // centrifuge lower double word
> + get_cpu_vsrl(src, a->vra + 32);
> + get_cpu_vsrl(mask, a->vrb + 32);
> + gen_helper_cfuged(tgt, src, mask);
> + set_cpu_vsrl(a->vrt + 32, tgt);
> +
> + // centrifuge higher double word
> + get_cpu_vsrh(src, a->vra + 32);
> + get_cpu_vsrh(mask, a->vrb + 32);
> + gen_helper_cfuged(tgt, src, mask);
> + set_cpu_vsrh(a->vrt + 32, tgt);
> +
> + tcg_temp_free_i64(tgt);
> + tcg_temp_free_i64(src);
> + tcg_temp_free_i64(mask);
> +
> + return true;
> +}
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 22/23] target/ppc: Move addpcis to decodetree
2021-05-17 20:50 ` [PATCH v5 22/23] target/ppc: Move addpcis to decodetree matheus.ferst
@ 2021-05-18 0:53 ` David Gibson
2021-05-18 9:55 ` Richard Henderson
1 sibling, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:53 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 3613 bytes --]
On Mon, May 17, 2021 at 05:50:24PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/insn32.decode | 6 ++++++
> target/ppc/translate.c | 9 ---------
> target/ppc/translate/fixedpoint-impl.c.inc | 7 +++++++
> 3 files changed, 13 insertions(+), 9 deletions(-)
>
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index 77edf407ab..93e5d44d9e 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -23,6 +23,10 @@
> %ds_si 2:s14 !function=times_4
> @DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
>
> +&DX rt d
> +%dx_d 6:s10 16:5 0:1
> +@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
> +
> &VX vrt vra vrb
> @VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
>
> @@ -90,6 +94,8 @@ STDUX 011111 ..... ..... ..... 0010110101 - @X
> ADDI 001110 ..... ..... ................ @D
> ADDIS 001111 ..... ..... ................ @D
>
> +ADDPCIS 010011 ..... ..... .......... 00010 . @DX
> +
> ## Fixed-Point Logical Instructions
>
> CFUGED 011111 ..... ..... ..... 0011011100 - @X
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index f56ed5866e..aef01af396 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -1865,14 +1865,6 @@ static void gen_addic_(DisasContext *ctx)
> gen_op_addic(ctx, 1);
> }
>
> -/* addpcis */
> -static void gen_addpcis(DisasContext *ctx)
> -{
> - target_long d = DX(ctx->opcode);
> -
> - tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16));
> -}
> -
> static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
> TCGv arg2, int sign, int compute_ov)
> {
> @@ -7745,7 +7737,6 @@ GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
> GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
> GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
> GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
> -GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
> GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
> GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
> GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
> diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
> index 4038143efb..4f257a931c 100644
> --- a/target/ppc/translate/fixedpoint-impl.c.inc
> +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> @@ -194,6 +194,13 @@ static bool trans_ADDIS(DisasContext *ctx, arg_D *a)
> return trans_ADDI(ctx, a);
> }
>
> +static bool trans_ADDPCIS(DisasContext *ctx, arg_DX *a)
> +{
> + REQUIRE_INSNS_FLAGS2(ctx, ISA300);
> + tcg_gen_movi_tl(cpu_gpr[a->rt], ctx->base.pc_next + (a->d<<16));
> + return true;
> +}
> +
> static bool trans_INVALID(DisasContext *ctx, arg_INVALID *a)
> {
> gen_invalid(ctx);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree
2021-05-17 20:50 ` [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli " matheus.ferst
@ 2021-05-18 0:56 ` David Gibson
2021-05-18 10:12 ` Richard Henderson
1 sibling, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 0:56 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 6384 bytes --]
On Mon, May 17, 2021 at 05:50:25PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/insn32.decode | 14 ++++++
> target/ppc/translate.c | 52 ----------------------
> target/ppc/translate/fixedpoint-impl.c.inc | 31 +++++++++++++
> 3 files changed, 45 insertions(+), 52 deletions(-)
>
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index 93e5d44d9e..9fd8d6b817 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -20,6 +20,10 @@
> &D rt ra si:int64_t
> @D ...... rt:5 ra:5 si:s16 &D
>
> +&D_bf bf l:bool ra imm
> +@D_bfs ...... bf:3 - l:1 ra:5 imm:s16 &D_bf
> +@D_bfu ...... bf:3 - l:1 ra:5 imm:16 &D_bf
> +
> %ds_si 2:s14 !function=times_4
> @DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
>
> @@ -36,6 +40,9 @@
> &X_bi rt bi
> @X_bi ...... rt:5 bi:5 ----- .......... - &X_bi
>
> +&X_bfl bf l:bool ra rb
> +@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl
> +
> ### Fixed-Point Load Instructions
>
> LBZ 100010 ..... ..... ................ @D
> @@ -89,6 +96,13 @@ STDU 111110 ..... ..... ..............01 @DS
> STDX 011111 ..... ..... ..... 0010010101 - @X
> STDUX 011111 ..... ..... ..... 0010110101 - @X
>
> +### Fixed-Point Compare Instructions
> +
> +CMP 011111 ... - . ..... ..... 0000000000 - @X_bfl
> +CMPL 011111 ... - . ..... ..... 0000100000 - @X_bfl
> +CMPI 001011 ... - . ..... ................ @D_bfs
> +CMPLI 001010 ... - . ..... ................ @D_bfu
> +
> ### Fixed-Point Arithmetic Instructions
>
> ADDI 001110 ..... ..... ................ @D
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index aef01af396..3fe58d0386 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -1575,54 +1575,6 @@ static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
> }
> }
>
> -/* cmp */
> -static void gen_cmp(DisasContext *ctx)
> -{
> - if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
> - gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
> - 1, crfD(ctx->opcode));
> - } else {
> - gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
> - 1, crfD(ctx->opcode));
> - }
> -}
> -
> -/* cmpi */
> -static void gen_cmpi(DisasContext *ctx)
> -{
> - if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
> - gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
> - 1, crfD(ctx->opcode));
> - } else {
> - gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
> - 1, crfD(ctx->opcode));
> - }
> -}
> -
> -/* cmpl */
> -static void gen_cmpl(DisasContext *ctx)
> -{
> - if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
> - gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
> - 0, crfD(ctx->opcode));
> - } else {
> - gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
> - 0, crfD(ctx->opcode));
> - }
> -}
> -
> -/* cmpli */
> -static void gen_cmpli(DisasContext *ctx)
> -{
> - if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
> - gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
> - 0, crfD(ctx->opcode));
> - } else {
> - gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
> - 0, crfD(ctx->opcode));
> - }
> -}
> -
> /* cmprb - range comparison: isupper, isaplha, islower*/
> static void gen_cmprb(DisasContext *ctx)
> {
> @@ -7725,10 +7677,6 @@ GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310),
> GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310),
> #endif
> GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
> -GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
> -GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
> -GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
> -GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
> #if defined(TARGET_PPC64)
> GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
> #endif
> diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
> index 4f257a931c..49c8993333 100644
> --- a/target/ppc/translate/fixedpoint-impl.c.inc
> +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> @@ -165,6 +165,37 @@ TRANS64(STDU, do_ldst_D, true, true, MO_Q)
> TRANS64(STDUX, do_ldst_X, true, true, MO_Q)
> TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_Q)
>
> +/*
> + * Fixed-Point Compare Instructions
> + */
> +
> +static bool do_cmp_X(DisasContext *ctx, arg_X_bfl *a, bool s)
> +{
> + REQUIRE_INSNS_FLAGS(ctx, INTEGER);
> + if(a->l && (ctx->insns_flags & PPC_64B)) {
> + gen_op_cmp(cpu_gpr[a->ra], cpu_gpr[a->rb], s, a->bf);
> + } else {
> + gen_op_cmp32(cpu_gpr[a->ra], cpu_gpr[a->rb], s, a->bf);
> + }
> + return true;
> +}
> +
> +static bool do_cmp_D(DisasContext *ctx, arg_D_bf *a, bool s)
> +{
> + REQUIRE_INSNS_FLAGS(ctx, INTEGER);
> + if(a->l && (ctx->insns_flags & PPC_64B)) {
> + gen_op_cmp(cpu_gpr[a->ra], tcg_constant_tl(a->imm), s, a->bf);
> + } else {
> + gen_op_cmp32(cpu_gpr[a->ra], tcg_constant_tl(a->imm), s, a->bf);
> + }
> + return true;
> +}
> +
> +TRANS(CMP, do_cmp_X, true);
> +TRANS(CMPL, do_cmp_X, false);
> +TRANS(CMPI, do_cmp_D, true);
> +TRANS(CMPLI, do_cmp_D, false);
> +
> /*
> * Fixed-Point Arithmetic Instructions
> */
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
` (22 preceding siblings ...)
2021-05-17 20:50 ` [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli " matheus.ferst
@ 2021-05-18 3:58 ` David Gibson
23 siblings, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-18 3:58 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 738 bytes --]
On Mon, May 17, 2021 at 05:50:02PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
>
> This series provides the basic infrastructure for adding the new 32/64-bit
> instructions in Power ISA 3.1 to target/ppc.
Well, I had applied them all, but I've now pulled patch 10 and onwards
out again, because it broke compile (there is no variable 'pc' in the
place that you use it).
Please make sure you do an (all targets) compile check at the *very
minimum* before posting in future.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 19/23] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions
2021-05-17 20:50 ` [PATCH v5 19/23] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions matheus.ferst
2021-05-18 0:49 ` David Gibson
@ 2021-05-18 9:48 ` Richard Henderson
1 sibling, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-05-18 9:48 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lagarcia, bruno.larsen, luis.pires, f4bug, david
On 5/17/21 3:50 PM, matheus.ferst@eldorado.org.br wrote:
> + if(neg) {
Missing space.
r~
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 21/23] target/ppc: Implement vcfuged instruction
2021-05-17 20:50 ` [PATCH v5 21/23] target/ppc: Implement vcfuged instruction matheus.ferst
2021-05-18 0:52 ` David Gibson
@ 2021-05-18 9:54 ` Richard Henderson
1 sibling, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-05-18 9:54 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lagarcia, bruno.larsen, luis.pires, f4bug, david
On 5/17/21 3:50 PM, matheus.ferst@eldorado.org.br wrote:
> + // centrifuge lower double word
No c++ style comments.
r~
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 22/23] target/ppc: Move addpcis to decodetree
2021-05-17 20:50 ` [PATCH v5 22/23] target/ppc: Move addpcis to decodetree matheus.ferst
2021-05-18 0:53 ` David Gibson
@ 2021-05-18 9:55 ` Richard Henderson
1 sibling, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-05-18 9:55 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lagarcia, bruno.larsen, luis.pires, f4bug, david
On 5/17/21 3:50 PM, matheus.ferst@eldorado.org.br wrote:
> + tcg_gen_movi_tl(cpu_gpr[a->rt], ctx->base.pc_next + (a->d<<16));
Missing spaces around <<.
r~
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree
2021-05-17 20:50 ` [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli " matheus.ferst
2021-05-18 0:56 ` David Gibson
@ 2021-05-18 10:12 ` Richard Henderson
2021-05-21 17:25 ` Matheus K. Ferst
1 sibling, 1 reply; 57+ messages in thread
From: Richard Henderson @ 2021-05-18 10:12 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lagarcia, bruno.larsen, luis.pires, f4bug, david
On 5/17/21 3:50 PM, matheus.ferst@eldorado.org.br wrote:
> + if(a->l && (ctx->insns_flags & PPC_64B)) {
Space after IF.
If I look back to the 6xx manual, I see
NOTE: If L = 1, the instruction form is invalid.
The fact that we're allowing L=1 for ppc32 is an existing bug, afaics. We
should fix that.
r~
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree
2021-05-18 10:12 ` Richard Henderson
@ 2021-05-21 17:25 ` Matheus K. Ferst
2021-05-24 18:51 ` Richard Henderson
0 siblings, 1 reply; 57+ messages in thread
From: Matheus K. Ferst @ 2021-05-21 17:25 UTC (permalink / raw)
To: Richard Henderson, qemu-devel, qemu-ppc
Cc: lagarcia, luis.pires, f4bug, david
On 18/05/2021 07:12, Richard Henderson wrote:
> On 5/17/21 3:50 PM, matheus.ferst@eldorado.org.br wrote:
>> + if(a->l && (ctx->insns_flags & PPC_64B)) {
>
> Space after IF.
> > If I look back to the 6xx manual, I see
>
> NOTE: If L = 1, the instruction form is invalid.
>
> The fact that we're allowing L=1 for ppc32 is an existing bug, afaics.
> We should fix that.
>
>
> r~
The previous commit on this line in translate.c says that "on most 32bit
CPUs we should always treat the compare as 32bit compare, as the CPU
will ignore the L bit", so maybe it was intentional. Should we change it
anyway?
--
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software Júnior
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree
2021-05-21 17:25 ` Matheus K. Ferst
@ 2021-05-24 18:51 ` Richard Henderson
2021-05-26 15:17 ` Matheus K. Ferst
0 siblings, 1 reply; 57+ messages in thread
From: Richard Henderson @ 2021-05-24 18:51 UTC (permalink / raw)
To: Matheus K. Ferst, qemu-devel, qemu-ppc; +Cc: lagarcia, luis.pires, f4bug, david
On 5/21/21 10:25 AM, Matheus K. Ferst wrote:
> On 18/05/2021 07:12, Richard Henderson wrote:
>> On 5/17/21 3:50 PM, matheus.ferst@eldorado.org.br wrote:
>>> + if(a->l && (ctx->insns_flags & PPC_64B)) {
>>
>> Space after IF.
>> > If I look back to the 6xx manual, I see
>>
>> NOTE: If L = 1, the instruction form is invalid.
>>
>> The fact that we're allowing L=1 for ppc32 is an existing bug, afaics. We
>> should fix that.
>>
>>
>> r~
>
> The previous commit on this line in translate.c says that "on most 32bit CPUs
> we should always treat the compare as 32bit compare, as the CPU will ignore the
> L bit", so maybe it was intentional. Should we change it anyway?
The actual change of 36f48d9c78c is about NARROW_MODE, which is about the
MSR.SF bit, and is correct.
The commit message mentions the e500mc specifically does check the L bit, and
then hand-waves about the others not checking. But the text I found in the 6xx
manual says that one checks too.
I wonder if the IBM folk can shed any further light on this?
r~
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree
2021-05-24 18:51 ` Richard Henderson
@ 2021-05-26 15:17 ` Matheus K. Ferst
2021-05-26 16:11 ` Richard Henderson
2021-05-27 1:11 ` David Gibson
0 siblings, 2 replies; 57+ messages in thread
From: Matheus K. Ferst @ 2021-05-26 15:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel, qemu-ppc
Cc: lagarcia, luis.pires, f4bug, david
On 24/05/2021 15:51, Richard Henderson wrote:
> On 5/21/21 10:25 AM, Matheus K. Ferst wrote:
>> On 18/05/2021 07:12, Richard Henderson wrote:
>>> On 5/17/21 3:50 PM, matheus.ferst@eldorado.org.br wrote:
>>>> + if(a->l && (ctx->insns_flags & PPC_64B)) {
>>>
>>> Space after IF.
>>> > If I look back to the 6xx manual, I see
>>>
>>> NOTE: If L = 1, the instruction form is invalid.
>>>
>>> The fact that we're allowing L=1 for ppc32 is an existing bug,
>>> afaics. We should fix that.
>>>
>>>
>>> r~
>>
>> The previous commit on this line in translate.c says that "on most
>> 32bit CPUs we should always treat the compare as 32bit compare, as the
>> CPU will ignore the L bit", so maybe it was intentional. Should we
>> change it anyway?
>
> The actual change of 36f48d9c78c is about NARROW_MODE, which is about
> the MSR.SF bit, and is correct.
>
> The commit message mentions the e500mc specifically does check the L
> bit, and then hand-waves about the others not checking. But the text I
> found in the 6xx manual says that one checks too.
>
> I wonder if the IBM folk can shed any further light on this?
>
>
> r~
I was pointed to the 601 manual, which says:
"While the PowerPC architecture specifies that the value in the L field
determines whether the operands are treated as 32- or 64-bit values, the
601 ignores the value in the L field and treats the operands as 32-bit
values."
There is also a section in Appendix B called "Reserved Bits in
Instructions", which says:
"These are shown with '/'s in the instruction opcode definitions. In the
POWER architecture such bits are ignored by the processor. In PowerPC
architecture they must be 0 or the instruction form is invalid. In
several cases the PowerPC architecture assumes that such bits in POWER
instructions are indeed 0. The cases include the following:
- cmpi, cmp, cmpli, and cmpl assume that bit 10 in the POWER
instructions is 0.
- mtspr and mfspr assume that bits 16–20 in the POWER instructions are 0."
Searching the manuals for other processors, I identified that the
manuals for 405, 440, e500, and e500mc explicit says that the L bit
should always be 0, and manuals for 603e, 604, 604e, 740/745/750/755,
750CX, 750CL, 750FX, 7400/7410, 7447/7447A/7448/7450/7455, e300, and
e600 list the bit L in operand syntax but do not mention any
restrictions on its value.
Alfredo Dal Ava Junior (adalva) did some tests for us on his G4 MacBook,
confirming that the bit is ignored in PowerPC 7447A v1.2, one of which
the manual does not specify the behavior, but I don't know if can assume
the same for other processors.
If we do bother to emulate the specific behavior for each CPU, what
would be the default for those whose manual is not explicit and we
cannot test? Also, I not sure how to check for it, do we need a new
POWERPC_FLAG in pcc->flags?
--
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software Júnior
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree
2021-05-26 15:17 ` Matheus K. Ferst
@ 2021-05-26 16:11 ` Richard Henderson
2021-05-27 1:11 ` David Gibson
1 sibling, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-05-26 16:11 UTC (permalink / raw)
To: Matheus K. Ferst, qemu-devel, qemu-ppc; +Cc: lagarcia, luis.pires, f4bug, david
On 5/26/21 8:17 AM, Matheus K. Ferst wrote:
> On 24/05/2021 15:51, Richard Henderson wrote:
>> On 5/21/21 10:25 AM, Matheus K. Ferst wrote:
>>> On 18/05/2021 07:12, Richard Henderson wrote:
>>>> On 5/17/21 3:50 PM, matheus.ferst@eldorado.org.br wrote:
>>>>> + if(a->l && (ctx->insns_flags & PPC_64B)) {
>>>>
>>>> Space after IF.
>>>> > If I look back to the 6xx manual, I see
>>>>
>>>> NOTE: If L = 1, the instruction form is invalid.
>>>>
>>>> The fact that we're allowing L=1 for ppc32 is an existing bug, afaics. We
>>>> should fix that.
>>>>
>>>>
>>>> r~
>>>
>>> The previous commit on this line in translate.c says that "on most 32bit
>>> CPUs we should always treat the compare as 32bit compare, as the CPU will
>>> ignore the L bit", so maybe it was intentional. Should we change it anyway?
>>
>> The actual change of 36f48d9c78c is about NARROW_MODE, which is about the
>> MSR.SF bit, and is correct.
>>
>> The commit message mentions the e500mc specifically does check the L bit, and
>> then hand-waves about the others not checking. But the text I found in the
>> 6xx manual says that one checks too.
>>
>> I wonder if the IBM folk can shed any further light on this?
>>
>>
>> r~
>
> I was pointed to the 601 manual, which says:
>
> "While the PowerPC architecture specifies that the value in the L field
> determines whether the operands are treated as 32- or 64-bit values, the 601
> ignores the value in the L field and treats the operands as 32-bit values."
>
> There is also a section in Appendix B called "Reserved Bits in Instructions",
> which says:
>
> "These are shown with '/'s in the instruction opcode definitions. In the POWER
> architecture such bits are ignored by the processor. In PowerPC architecture
> they must be 0 or the instruction form is invalid. In several cases the PowerPC
> architecture assumes that such bits in POWER instructions are indeed 0. The
> cases include the following:
> - cmpi, cmp, cmpli, and cmpl assume that bit 10 in the POWER instructions is 0.
> - mtspr and mfspr assume that bits 16–20 in the POWER instructions are 0."
>
> Searching the manuals for other processors, I identified that the manuals for
> 405, 440, e500, and e500mc explicit says that the L bit should always be 0, and
> manuals for 603e, 604, 604e, 740/745/750/755, 750CX, 750CL, 750FX, 7400/7410,
> 7447/7447A/7448/7450/7455, e300, and e600 list the bit L in operand syntax but
> do not mention any restrictions on its value.
>
> Alfredo Dal Ava Junior (adalva) did some tests for us on his G4 MacBook,
> confirming that the bit is ignored in PowerPC 7447A v1.2, one of which the
> manual does not specify the behavior, but I don't know if can assume the same
> for other processors.
>
> If we do bother to emulate the specific behavior for each CPU, what would be
> the default for those whose manual is not explicit and we cannot test? Also, I
> not sure how to check for it, do we need a new POWERPC_FLAG in pcc->flags?
Thanks for the research.
There's an argument for following the architecture, even when implementations
vary. Especially when implementations very, as this makes testing with qemu
more likely to catch software bugs.
There's another argument for following implementations. I would generally
reserve this interpretation for historical cpus, where we are trying to emulate
something specific (e.g. a games console) where the legacy software relies on
specific behavior.
I'll let David have the final call on this, but my inclination is to follow the
architecture and require 0s for reserved bits.
r~
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree
2021-05-26 15:17 ` Matheus K. Ferst
2021-05-26 16:11 ` Richard Henderson
@ 2021-05-27 1:11 ` David Gibson
1 sibling, 0 replies; 57+ messages in thread
From: David Gibson @ 2021-05-27 1:11 UTC (permalink / raw)
To: Matheus K. Ferst
Cc: Richard Henderson, qemu-devel, f4bug, luis.pires, qemu-ppc, lagarcia
[-- Attachment #1: Type: text/plain, Size: 3521 bytes --]
On Wed, May 26, 2021 at 12:17:48PM -0300, Matheus K. Ferst wrote:
> On 24/05/2021 15:51, Richard Henderson wrote:
> > On 5/21/21 10:25 AM, Matheus K. Ferst wrote:
> > > On 18/05/2021 07:12, Richard Henderson wrote:
> > > > On 5/17/21 3:50 PM, matheus.ferst@eldorado.org.br wrote:
> > > > > + if(a->l && (ctx->insns_flags & PPC_64B)) {
> > > >
> > > > Space after IF.
> > > > > If I look back to the 6xx manual, I see
> > > >
> > > > NOTE: If L = 1, the instruction form is invalid.
> > > >
> > > > The fact that we're allowing L=1 for ppc32 is an existing bug,
> > > > afaics. We should fix that.
> > > >
> > > >
> > > > r~
> > >
> > > The previous commit on this line in translate.c says that "on most
> > > 32bit CPUs we should always treat the compare as 32bit compare, as
> > > the CPU will ignore the L bit", so maybe it was intentional. Should
> > > we change it anyway?
> >
> > The actual change of 36f48d9c78c is about NARROW_MODE, which is about
> > the MSR.SF bit, and is correct.
> >
> > The commit message mentions the e500mc specifically does check the L
> > bit, and then hand-waves about the others not checking. But the text I
> > found in the 6xx manual says that one checks too.
> >
> > I wonder if the IBM folk can shed any further light on this?
> >
> >
> > r~
>
> I was pointed to the 601 manual, which says:
>
> "While the PowerPC architecture specifies that the value in the L field
> determines whether the operands are treated as 32- or 64-bit values, the 601
> ignores the value in the L field and treats the operands as 32-bit values."
>
> There is also a section in Appendix B called "Reserved Bits in
> Instructions", which says:
>
> "These are shown with '/'s in the instruction opcode definitions. In the
> POWER architecture such bits are ignored by the processor. In PowerPC
> architecture they must be 0 or the instruction form is invalid. In several
> cases the PowerPC architecture assumes that such bits in POWER instructions
> are indeed 0. The cases include the following:
> - cmpi, cmp, cmpli, and cmpl assume that bit 10 in the POWER instructions is
> 0.
> - mtspr and mfspr assume that bits 16–20 in the POWER instructions are 0."
>
> Searching the manuals for other processors, I identified that the manuals
> for 405, 440, e500, and e500mc explicit says that the L bit should always be
> 0, and manuals for 603e, 604, 604e, 740/745/750/755, 750CX, 750CL, 750FX,
> 7400/7410, 7447/7447A/7448/7450/7455, e300, and e600 list the bit L in
> operand syntax but do not mention any restrictions on its value.
>
> Alfredo Dal Ava Junior (adalva) did some tests for us on his G4 MacBook,
> confirming that the bit is ignored in PowerPC 7447A v1.2, one of which the
> manual does not specify the behavior, but I don't know if can assume the
> same for other processors.
>
> If we do bother to emulate the specific behavior for each CPU, what would be
> the default for those whose manual is not explicit and we cannot test? Also,
> I not sure how to check for it, do we need a new POWERPC_FLAG in pcc->flags?
My inclination would be to make L=1 program check on all 32-bit cpus
for now, and if someone pipes up with a guest broken because it
assumes L=1 is ignored, we can fix it then.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 57+ messages in thread
end of thread, other threads:[~2021-05-27 1:49 UTC | newest]
Thread overview: 57+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
2021-05-17 20:50 ` [PATCH v5 01/23] target/ppc: Introduce gen_icount_io_start matheus.ferst
2021-05-18 0:13 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 02/23] target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE matheus.ferst
2021-05-18 0:14 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 03/23] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN matheus.ferst
2021-05-18 0:15 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 04/23] target/ppc: Remove DisasContext.exception matheus.ferst
2021-05-18 0:17 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 05/23] target/ppc: Move single-step check to ppc_tr_tb_stop matheus.ferst
2021-05-18 0:19 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 06/23] target/ppc: Tidy exception vs exit_tb matheus.ferst
2021-05-18 0:19 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 07/23] target/ppc: Mark helper_raise_exception* as noreturn matheus.ferst
2021-05-18 0:20 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 08/23] target/ppc: Use translator_loop_temp_check matheus.ferst
2021-05-18 0:20 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 09/23] target/ppc: Introduce macros to check isa extensions matheus.ferst
2021-05-18 0:21 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 10/23] target/ppc: Move page crossing check to ppc_tr_translate_insn matheus.ferst
2021-05-18 0:23 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 11/23] target/ppc: Add infrastructure for prefixed insns matheus.ferst
2021-05-18 0:25 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 12/23] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI matheus.ferst
2021-05-18 0:35 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 13/23] target/ppc: Implement PNOP matheus.ferst
2021-05-18 0:36 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 14/23] TCG: add tcg_constant_tl matheus.ferst
2021-05-18 0:37 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 15/23] target/ppc: Move D/DS/X-form integer loads to decodetree matheus.ferst
2021-05-18 0:44 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 16/23] target/ppc: Implement prefixed integer load instructions matheus.ferst
2021-05-18 0:45 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 17/23] target/ppc: Move D/DS/X-form integer stores to decodetree matheus.ferst
2021-05-18 0:47 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 18/23] target/ppc: Implement prefixed integer store instructions matheus.ferst
2021-05-18 0:47 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 19/23] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions matheus.ferst
2021-05-18 0:49 ` David Gibson
2021-05-18 9:48 ` Richard Henderson
2021-05-17 20:50 ` [PATCH v5 20/23] target/ppc: Implement cfuged instruction matheus.ferst
2021-05-18 0:51 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 21/23] target/ppc: Implement vcfuged instruction matheus.ferst
2021-05-18 0:52 ` David Gibson
2021-05-18 9:54 ` Richard Henderson
2021-05-17 20:50 ` [PATCH v5 22/23] target/ppc: Move addpcis to decodetree matheus.ferst
2021-05-18 0:53 ` David Gibson
2021-05-18 9:55 ` Richard Henderson
2021-05-17 20:50 ` [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli " matheus.ferst
2021-05-18 0:56 ` David Gibson
2021-05-18 10:12 ` Richard Henderson
2021-05-21 17:25 ` Matheus K. Ferst
2021-05-24 18:51 ` Richard Henderson
2021-05-26 15:17 ` Matheus K. Ferst
2021-05-26 16:11 ` Richard Henderson
2021-05-27 1:11 ` David Gibson
2021-05-18 3:58 ` [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions David Gibson
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.