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([2a01:cb1d:8a0a:f500:48c1:8eab:256a:caf9]) by smtp.gmail.com with ESMTPSA id i16sm23230821wmb.36.2020.01.14.23.22.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 14 Jan 2020 23:22:08 -0800 (PST) Subject: Re: [PATCH 2/3] linux-user/i386: Split out gen_signal To: Richard Henderson , qemu-devel@nongnu.org References: <20200114210921.11216-1-richard.henderson@linaro.org> <20200114210921.11216-3-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Wed, 15 Jan 2020 08:22:06 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20200114210921.11216-3-richard.henderson@linaro.org> Content-Language: en-US X-MC-Unique: 0NTmplKfN0arFQOolyzIPA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, riku.voipio@iki.fi, laurent@vivier.eu, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 1/14/20 10:09 PM, Richard Henderson wrote: > This is a bit tidier than open-coding the 5 lines necessary > to initialize the target_siginfo_t. In addition, this zeros > the remaining bytes of the target_siginfo_t, rather than > passing in garbage. >=20 > Signed-off-by: Richard Henderson > --- > linux-user/i386/cpu_loop.c | 93 ++++++++++++++------------------------ > 1 file changed, 33 insertions(+), 60 deletions(-) >=20 > diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c > index 024b6f4d58..e217cca5ee 100644 > --- a/linux-user/i386/cpu_loop.c > +++ b/linux-user/i386/cpu_loop.c > @@ -81,13 +81,23 @@ static void set_idt(int n, unsigned int dpl) > } > #endif > =20 > +static void gen_signal(CPUX86State *env, int sig, int code, abi_ptr addr= ) > +{ > + target_siginfo_t info =3D { > + .si_signo =3D sig, > + .si_code =3D code, > + ._sifields._sigfault._addr =3D addr > + }; > + > + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); > +} > + > void cpu_loop(CPUX86State *env) > { > CPUState *cs =3D env_cpu(env); > int trapnr; > abi_ulong pc; > abi_ulong ret; > - target_siginfo_t info; > =20 > for(;;) { > cpu_exec_start(cs); > @@ -134,70 +144,45 @@ void cpu_loop(CPUX86State *env) > #endif > case EXCP0B_NOSEG: > case EXCP0C_STACK: > - info.si_signo =3D TARGET_SIGBUS; > - info.si_errno =3D 0; > - info.si_code =3D TARGET_SI_KERNEL; > - info._sifields._sigfault._addr =3D 0; > - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); > + gen_signal(env, TARGET_SIGBUS, TARGET_SI_KERNEL, 0); > break; > case EXCP0D_GPF: > /* XXX: potential problem if ABI32 */ > #ifndef TARGET_X86_64 > if (env->eflags & VM_MASK) { > handle_vm86_fault(env); > - } else > -#endif > - { > - info.si_signo =3D TARGET_SIGSEGV; > - info.si_errno =3D 0; > - info.si_code =3D TARGET_SI_KERNEL; > - info._sifields._sigfault._addr =3D 0; > - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); > + break; > } > +#endif > + gen_signal(env, TARGET_SIGSEGV, TARGET_SI_KERNEL, 0); > break; > case EXCP0E_PAGE: > - info.si_signo =3D TARGET_SIGSEGV; > - info.si_errno =3D 0; > - if (!(env->error_code & 1)) > - info.si_code =3D TARGET_SEGV_MAPERR; > - else > - info.si_code =3D TARGET_SEGV_ACCERR; > - info._sifields._sigfault._addr =3D env->cr[2]; > - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); > + gen_signal(env, TARGET_SIGSEGV, > + (env->error_code & 1 ? > + TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR), > + env->cr[2]); > break; > case EXCP00_DIVZ: > #ifndef TARGET_X86_64 > if (env->eflags & VM_MASK) { > handle_vm86_trap(env, trapnr); > - } else > -#endif > - { > - /* division by zero */ > - info.si_signo =3D TARGET_SIGFPE; > - info.si_errno =3D 0; > - info.si_code =3D TARGET_FPE_INTDIV; > - info._sifields._sigfault._addr =3D env->eip; > - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); > + break; > } > +#endif > + gen_signal(env, TARGET_SIGFPE, TARGET_FPE_INTDIV, env->eip); > break; > case EXCP01_DB: > case EXCP03_INT3: > #ifndef TARGET_X86_64 > if (env->eflags & VM_MASK) { > handle_vm86_trap(env, trapnr); > - } else > + break; > + } > #endif > - { > - info.si_signo =3D TARGET_SIGTRAP; > - info.si_errno =3D 0; > - if (trapnr =3D=3D EXCP01_DB) { > - info.si_code =3D TARGET_TRAP_BRKPT; > - info._sifields._sigfault._addr =3D env->eip; > - } else { > - info.si_code =3D TARGET_SI_KERNEL; > - info._sifields._sigfault._addr =3D 0; > - } > - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); > + if (trapnr =3D=3D EXCP01_DB) { > + gen_signal(env, TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->= eip); > + } else { > + gen_signal(env, TARGET_SIGTRAP, TARGET_SI_KERNEL, 0); > } > break; > case EXCP04_INTO: > @@ -205,31 +190,19 @@ void cpu_loop(CPUX86State *env) > #ifndef TARGET_X86_64 > if (env->eflags & VM_MASK) { > handle_vm86_trap(env, trapnr); > - } else > -#endif > - { > - info.si_signo =3D TARGET_SIGSEGV; > - info.si_errno =3D 0; > - info.si_code =3D TARGET_SI_KERNEL; > - info._sifields._sigfault._addr =3D 0; > - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); > + break; > } > +#endif > + gen_signal(env, TARGET_SIGSEGV, TARGET_SI_KERNEL, 0); > break; > case EXCP06_ILLOP: > - info.si_signo =3D TARGET_SIGILL; > - info.si_errno =3D 0; > - info.si_code =3D TARGET_ILL_ILLOPN; > - info._sifields._sigfault._addr =3D env->eip; > - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); > + gen_signal(env, TARGET_SIGILL, TARGET_ILL_ILLOPN, env->eip); > break; > case EXCP_INTERRUPT: > /* just indicate that signals should be handled asap */ > break; > case EXCP_DEBUG: > - info.si_signo =3D TARGET_SIGTRAP; > - info.si_errno =3D 0; > - info.si_code =3D TARGET_TRAP_BRKPT; > - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); > + gen_signal(env, TARGET_SIGTRAP, TARGET_TRAP_BRKPT, 0); > break; > case EXCP_ATOMIC: > cpu_exec_step_atomic(cs); >=20 Reviewed-by: Philippe Mathieu-Daud=C3=A9