From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40284) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQYwZ-0008Sc-VR for qemu-devel@nongnu.org; Wed, 06 Jun 2018 09:57:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fQYwU-0000Wp-7h for qemu-devel@nongnu.org; Wed, 06 Jun 2018 09:57:44 -0400 Message-Id: In-Reply-To: References: From: BALATON Zoltan Date: Wed, 06 Jun 2018 15:31:48 +0200 Subject: [Qemu-devel] [PATCH v2 7/8] sm501: Do not clear read only bits when writing register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: Alexander Graf , David Gibson , Peter Maydell When writing a register that has read only bits besides reserved bits we have to avoid changing read only bits that may have non zero default values. Signed-off-by: BALATON Zoltan --- hw/display/sm501.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/display/sm501.c b/hw/display/sm501.c index e47be99..7ec1434 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -836,10 +836,10 @@ static void sm501_system_config_write(void *opaque, hwaddr addr, switch (addr) { case SM501_SYSTEM_CONTROL: - s->system_control = value & 0xE300B8F7; + s->system_control |= value & 0xEF00B8F7; break; case SM501_MISC_CONTROL: - s->misc_control = value & 0xFF7FFF20; + s->misc_control |= value & 0xFF7FFF10; break; case SM501_GPIO31_0_CONTROL: s->gpio_31_0_control = value; @@ -853,7 +853,7 @@ static void sm501_system_config_write(void *opaque, hwaddr addr, s->dram_control |= value & 0x7FFFFFC3; break; case SM501_ARBTRTN_CONTROL: - s->arbitration_control = value & 0x37777777; + s->arbitration_control = value & 0x37777777; break; case SM501_IRQ_MASK: s->irq_mask = value; -- 2.7.6