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[83.29.147.144]) by smtp.gmail.com with ESMTPSA id de3-20020a1709069bc300b0088be5f9843fsm1138776ejc.158.2023.01.31.04.34.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 04:34:15 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 932ebe66-a163-11ed-b63b-5f92e7d2e73a DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:user-agent:content-transfer-encoding:references :in-reply-to:date:cc:to:from:subject:message-id:from:to:cc:subject :date:message-id:reply-to; bh=rHkuxG+nSuICPPi7KodEiRosBEeuCix+OENZAvUeQVA=; b=g+T7mDATQy7IYOwckkooh1zbU7ylJdT2cfn9caLlxOejNK9YLb24nQ31v5ppki+1so 0z/1p/LwIMz+Y2tUv0nA5+IIpRljM7HHn7nZ7/GOjva/+so/ADrHItjTBpoET+8cW1II ctfLA1m7TBvIknZ59F18Zk8YF65K1FrSVxzg77oPoXrZikXWGAjIXJhQCgfKzcg67UgB bZLxmPBitWwc4ff/TKxRP8kvYq+nnmzNF8r3Mc4nuj0ln2svLZl8p6uhCz+X5ux1DR8h jAVAyQw+qDVTnLdi7uBQqvnl2C+sOH4YcXO3oPCVuWTV6OlxN75R7Hxk6vr6VBVunC5M bWEw== X-Google-DKIM-Signature: v=1; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.46.3 (3.46.3-1.fc37) MIME-Version: 1.0 On Mon, 2023-01-30 at 22:28 +0000, Julien Grall wrote: > Hi Oleksii, >=20 > On 30/01/2023 11:35, Oleksii wrote: > > Hi Julien, > > On Fri, 2023-01-27 at 16:02 +0000, Julien Grall wrote: > > > Hi Oleksii, > > >=20 > > > On 27/01/2023 13:59, Oleksii Kurochko wrote: > > > > The patch introduces macros: BUG(), WARN(), run_in_exception(), > > > > assert_failed. > > > >=20 > > > > The implementation uses "ebreak" instruction in combination > > > > with > > > > diffrent bug frame tables (for each type) which contains useful > > > > information. > > > >=20 > > > > Signed-off-by: Oleksii Kurochko > > > > --- > > > > Changes: > > > > =C2=A0=C2=A0=C2=A0 - Remove __ in define namings > > > > =C2=A0=C2=A0=C2=A0 - Update run_in_exception_handler() with > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 register void *fn_ asm(__stringify(B= UG_FN_REG)) =3D (fn); > > > > =C2=A0=C2=A0=C2=A0 - Remove bug_instr_t type and change it's usage = to uint32_t > > > > --- > > > > =C2=A0=C2=A0 xen/arch/riscv/include/asm/bug.h | 118 > > > > ++++++++++++++++++++++++++++ > > > > =C2=A0=C2=A0 xen/arch/riscv/traps.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 128 > > > > +++++++++++++++++++++++++++++++ > > > > =C2=A0=C2=A0 xen/arch/riscv/xen.lds.S=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 |=C2=A0 10 +++ > > > > =C2=A0=C2=A0 3 files changed, 256 insertions(+) > > > > =C2=A0=C2=A0 create mode 100644 xen/arch/riscv/include/asm/bug.h > > > >=20 > > > > diff --git a/xen/arch/riscv/include/asm/bug.h > > > > b/xen/arch/riscv/include/asm/bug.h > > > > new file mode 100644 > > > > index 0000000000..4b15d8eba6 > > > > --- /dev/null > > > > +++ b/xen/arch/riscv/include/asm/bug.h > > > > @@ -0,0 +1,118 @@ > > > > +/* SPDX-License-Identifier: GPL-2.0 */ > > > > +/* > > > > + * Copyright (C) 2012 Regents of the University of California > > > > + * Copyright (C) 2021-2023 Vates > > >=20 > > > I have to question the two copyrights here given that the > > > majority of > > > the code seems to be taken from the arm implementation (see > > > arch/arm/include/asm/bug.h). > > >=20 > > > With that said, we should consolidate the code rather than > > > duplicating > > > it on every architecture. > > >=20 > > Copyrights should be removed. They were taken from the previous > > implementation of bug.h for RISC-V so I just forgot to remove them. > >=20 > > It looks like we should have common bug.h for ARM and RISCV but I > > am > > not sure that I know how to do that better. > > Probably the code wants to be moved to xen/include/bug.h and using > > ifdef ARM && RISCV ... >=20 > Or you could introduce CONFIG_BUG_GENERIC or else, so it is easily=20 > selectable by other architecture. >=20 > > But still I am not sure that this is the best one option as at > > least we > > have different implementation for x86_64. >=20 > My main concern is the maintainance effort. For every bug, we would > need=20 > to fix it in two places. The risk is we may forget to fix one > architecture. > This is not a very ideal situation. >=20 > So I think sharing the header between RISC-V and Arm (or x86, see > below)=20 > is at least a must. We can do the 3rd architecture at a leisure pace. >=20 > One option would be to introduce asm-generic like Linux (IIRC this > was a=20 > suggestion from Andrew). This would also to share code between two of > the archs. >=20 > Also, from a brief look, the difference in implementation is mainly=20 > because on Arm we can't use %c (some version of GCC didn't support > it).=20 > Is this also the case on RISC-V? If not, you may want to consider to > use=20 > the x86 version. >=20 No, it shouldn't be an issue for RISC-V. I'll double check. Any way it should bug.h should be shared between archs so I am going to rework that in this patch series and sent the changes in the next version of the patch series. Thanks. ~Oleksii > Cheers, >=20