From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932609AbdELIjW (ORCPT ); Fri, 12 May 2017 04:39:22 -0400 Received: from mail-wm0-f67.google.com ([74.125.82.67]:34040 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932189AbdELIjT (ORCPT ); Fri, 12 May 2017 04:39:19 -0400 Subject: Re: [PATCH 2/2] KVM: nVMX: fix nEPT handling of guest page table accesses To: Xiao Guangrong , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: Peter Feiner , David Matlack , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , Xiao Guangrong , Wanpeng Li , kevin.tian@intel.com References: <1494501810-11822-1-git-send-email-pbonzini@redhat.com> <1494501810-11822-3-git-send-email-pbonzini@redhat.com> <4a02522c-50a1-0aa2-879c-98ba7631ffbe@gmail.com> From: Paolo Bonzini Message-ID: Date: Fri, 12 May 2017 10:39:12 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.0 MIME-Version: 1.0 In-Reply-To: <4a02522c-50a1-0aa2-879c-98ba7631ffbe@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/05/2017 09:38, Xiao Guangrong wrote: > CC Kevin as i am not sure if Intel is aware of this issue, it > breaks other hypervisors, e.g, Xen, as swell. It's actually more complicated. When EPT A/D bits are disabled, reads of the page tables behave as described in the manual; writes have both bit 0 and bit 1 set, while the manual suggests only bit 1 is set. Peter and David convinced me that it's a hypervisor bug, and I'm not surprised that Xen has the same issue. You have to disable EPT A/D bits for shadow EPT page tables when the L1 hypervisor is not using them. Paolo