diff for duplicates of <fe7c20fa689d3b9230be0b552f667c043d11ed75.1424849129.git.horms+renesas@verge.net.au>
diff --git a/a/1.txt b/N1/1.txt
index e73bbe8..fd706ee 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -37,7 +37,7 @@ index 8a09260..83c1c3c 100644
};
/* Variable factor clocks (DIV6) */
-+ vclk1_clk: vclk1_clk@e6150008 {
++ vclk1_clk: vclk1_clk at e6150008 {
+ compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+ reg = <0xe6150008 4>;
+ clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
@@ -47,7 +47,7 @@ index 8a09260..83c1c3c 100644
+ #clock-cells = <0>;
+ clock-output-names = "vclk1";
+ };
-+ vclk2_clk: vclk2_clk@e615000c {
++ vclk2_clk: vclk2_clk at e615000c {
+ compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+ reg = <0xe615000c 4>;
+ clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
@@ -57,28 +57,28 @@ index 8a09260..83c1c3c 100644
+ #clock-cells = <0>;
+ clock-output-names = "vclk2";
+ };
-+ fmsi_clk: fmsi_clk@e6150010 {
++ fmsi_clk: fmsi_clk at e6150010 {
+ compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+ reg = <0xe6150010 4>;
+ clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;
+ #clock-cells = <0>;
+ clock-output-names = "fmsi";
+ };
-+ fmso_clk: fmso_clk@e6150014 {
++ fmso_clk: fmso_clk at e6150014 {
+ compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+ reg = <0xe6150014 4>;
+ clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;
+ #clock-cells = <0>;
+ clock-output-names = "fmso";
+ };
-+ fsia_clk: fsia_clk@e6150018 {
++ fsia_clk: fsia_clk at e6150018 {
+ compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+ reg = <0xe6150018 4>;
+ clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;
+ #clock-cells = <0>;
+ clock-output-names = "fsia";
+ };
- sub_clk: sub_clk@e6150080 {
+ sub_clk: sub_clk at e6150080 {
compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe6150080 4>;
- clocks = <&pllc1_div2_clk>;
@@ -87,7 +87,7 @@ index 8a09260..83c1c3c 100644
#clock-cells = <0>;
clock-output-names = "sub";
};
-+ spu_clk: spu_clk@e6150084 {
++ spu_clk: spu_clk at e6150084 {
+ compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+ reg = <0xe6150084 4>;
+ clocks = <&pllc1_div2_clk>,
@@ -95,7 +95,7 @@ index 8a09260..83c1c3c 100644
+ #clock-cells = <0>;
+ clock-output-names = "spu";
+ };
-+ vou_clk: vou_clk@e6150088 {
++ vou_clk: vou_clk at e6150088 {
+ compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+ reg = <0xe6150088 4>;
+ clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,
@@ -103,7 +103,7 @@ index 8a09260..83c1c3c 100644
+ #clock-cells = <0>;
+ clock-output-names = "vou";
+ };
-+ stpro_clk: stpro_clk@e615009c {
++ stpro_clk: stpro_clk at e615009c {
+ compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+ reg = <0xe615009c 4>;
+ clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;
diff --git a/a/content_digest b/N1/content_digest
index da37c5c..5eb46f0 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -2,13 +2,13 @@
"ref\0cover.1424849129.git.horms+renesas\@verge.net.au\0"
]
[
- "From\0Simon Horman <horms+renesas\@verge.net.au>\0"
+ "From\0horms+renesas\@verge.net.au (Simon Horman)\0"
]
[
"Subject\0[PATCH 01/32] ARM: shmobile: r8a7740 dtsi: add remaining DIV6 clocks\0"
]
[
- "Date\0Thu, 26 Feb 2015 06:20:58 +0000\0"
+ "Date\0Thu, 26 Feb 2015 15:20:58 +0900\0"
]
[
"To\0linux-arm-kernel\@lists.infradead.org\0"
@@ -59,7 +59,7 @@
" \t\t};\n",
" \n",
" \t\t/* Variable factor clocks (DIV6) */\n",
- "+\t\tvclk1_clk: vclk1_clk\@e6150008 {\n",
+ "+\t\tvclk1_clk: vclk1_clk at e6150008 {\n",
"+\t\t\tcompatible = \"renesas,r8a7740-div6-clock\", \"renesas,cpg-div6-clock\";\n",
"+\t\t\treg = <0xe6150008 4>;\n",
"+\t\t\tclocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,\n",
@@ -69,7 +69,7 @@
"+\t\t\t#clock-cells = <0>;\n",
"+\t\t\tclock-output-names = \"vclk1\";\n",
"+\t\t};\n",
- "+\t\tvclk2_clk: vclk2_clk\@e615000c {\n",
+ "+\t\tvclk2_clk: vclk2_clk at e615000c {\n",
"+\t\t\tcompatible = \"renesas,r8a7740-div6-clock\", \"renesas,cpg-div6-clock\";\n",
"+\t\t\treg = <0xe615000c 4>;\n",
"+\t\t\tclocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,\n",
@@ -79,28 +79,28 @@
"+\t\t\t#clock-cells = <0>;\n",
"+\t\t\tclock-output-names = \"vclk2\";\n",
"+\t\t};\n",
- "+\t\tfmsi_clk: fmsi_clk\@e6150010 {\n",
+ "+\t\tfmsi_clk: fmsi_clk at e6150010 {\n",
"+\t\t\tcompatible = \"renesas,r8a7740-div6-clock\", \"renesas,cpg-div6-clock\";\n",
"+\t\t\treg = <0xe6150010 4>;\n",
"+\t\t\tclocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;\n",
"+\t\t\t#clock-cells = <0>;\n",
"+\t\t\tclock-output-names = \"fmsi\";\n",
"+\t\t};\n",
- "+\t\tfmso_clk: fmso_clk\@e6150014 {\n",
+ "+\t\tfmso_clk: fmso_clk at e6150014 {\n",
"+\t\t\tcompatible = \"renesas,r8a7740-div6-clock\", \"renesas,cpg-div6-clock\";\n",
"+\t\t\treg = <0xe6150014 4>;\n",
"+\t\t\tclocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;\n",
"+\t\t\t#clock-cells = <0>;\n",
"+\t\t\tclock-output-names = \"fmso\";\n",
"+\t\t};\n",
- "+\t\tfsia_clk: fsia_clk\@e6150018 {\n",
+ "+\t\tfsia_clk: fsia_clk at e6150018 {\n",
"+\t\t\tcompatible = \"renesas,r8a7740-div6-clock\", \"renesas,cpg-div6-clock\";\n",
"+\t\t\treg = <0xe6150018 4>;\n",
"+\t\t\tclocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;\n",
"+\t\t\t#clock-cells = <0>;\n",
"+\t\t\tclock-output-names = \"fsia\";\n",
"+\t\t};\n",
- " \t\tsub_clk: sub_clk\@e6150080 {\n",
+ " \t\tsub_clk: sub_clk at e6150080 {\n",
" \t\t\tcompatible = \"renesas,r8a7740-div6-clock\", \"renesas,cpg-div6-clock\";\n",
" \t\t\treg = <0xe6150080 4>;\n",
"-\t\t\tclocks = <&pllc1_div2_clk>;\n",
@@ -109,7 +109,7 @@
" \t\t\t#clock-cells = <0>;\n",
" \t\t\tclock-output-names = \"sub\";\n",
" \t\t};\n",
- "+\t\tspu_clk: spu_clk\@e6150084 {\n",
+ "+\t\tspu_clk: spu_clk at e6150084 {\n",
"+\t\t\tcompatible = \"renesas,r8a7740-div6-clock\", \"renesas,cpg-div6-clock\";\n",
"+\t\t\treg = <0xe6150084 4>;\n",
"+\t\t\tclocks = <&pllc1_div2_clk>,\n",
@@ -117,7 +117,7 @@
"+\t\t\t#clock-cells = <0>;\n",
"+\t\t\tclock-output-names = \"spu\";\n",
"+\t\t};\n",
- "+\t\tvou_clk: vou_clk\@e6150088 {\n",
+ "+\t\tvou_clk: vou_clk at e6150088 {\n",
"+\t\t\tcompatible = \"renesas,r8a7740-div6-clock\", \"renesas,cpg-div6-clock\";\n",
"+\t\t\treg = <0xe6150088 4>;\n",
"+\t\t\tclocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,\n",
@@ -125,7 +125,7 @@
"+\t\t\t#clock-cells = <0>;\n",
"+\t\t\tclock-output-names = \"vou\";\n",
"+\t\t};\n",
- "+\t\tstpro_clk: stpro_clk\@e615009c {\n",
+ "+\t\tstpro_clk: stpro_clk at e615009c {\n",
"+\t\t\tcompatible = \"renesas,r8a7740-div6-clock\", \"renesas,cpg-div6-clock\";\n",
"+\t\t\treg = <0xe615009c 4>;\n",
"+\t\t\tclocks = <&cpg_clocks R8A7740_CLK_PLLC0>;\n",
@@ -139,4 +139,4 @@
"2.1.4"
]
-b8a9535077d1cc4954caeda9289098772ba632332d965d862eb931bdebe780f8
+3daffb4883c56bb7c7dc1fa69b2f10e8a22a3f58c3fde9986ce2349255242564
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