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[24.4.73.83]) by smtp.gmail.com with ESMTPSA id s2sm6840686pjs.56.2021.10.13.09.20.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 Oct 2021 09:20:53 -0700 (PDT) Subject: Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci To: Philipp Tomsich , Vincent Palatin References: <20211007064751.608580-1-alistair.francis@opensource.wdc.com> <20211007064751.608580-12-alistair.francis@opensource.wdc.com> From: Vineet Gupta Message-ID: Date: Wed, 13 Oct 2021 09:20:51 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=vineetg@rivosinc.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Anup Patel , Richard Henderson , "qemu-devel@nongnu.org Developers" , Alistair Francis , Alistair Francis , Alistair Francis , Palmer Dabbelt , Jim Wilson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/13/21 6:49 AM, Philipp Tomsich wrote: > On Wed, 13 Oct 2021 at 15:44, Vincent Palatin wrote: >> >> On Wed, Oct 13, 2021 at 3:13 PM Philipp Tomsich >> wrote: >>> >>> I had a much simpler version initially (using 3 x mask/shift/or, for >>> 12 instructions after setup of constants), but took up the suggestion >>> to optimize based on haszero(v)... >>> Indeed this appears to not do what we expect, when there's only 0x01 >>> set in a byte. >>> >>> The less optimized form, with a single constant, that would still do >>> what we want is: >>> /* set high-bit for non-zero bytes */ >>> constant = dup_const_tl(MO_8, 0x7f); >>> tmp = v & constant; // AND >>> tmp += constant; // ADD >>> tmp |= v; // OR >>> /* extract high-bit to low-bit, for each word */ >>> tmp &= ~constant; // ANDC >>> tmp >>= 7; // SHR >>> /* multiply with 0xff to populate entire byte where the low-bit is set */ >>> tmp *= 0xff; // MUL >>> >>> I'll submit a patch with this one later today, once I had a chance to >>> pass this through a full test. >> >> >> Thanks for the insight. >> >> I have tried it, implemented as: >> ``` >> static void gen_orc_b(TCGv ret, TCGv source1) >> { >> TCGv tmp = tcg_temp_new(); >> TCGv constant = tcg_constant_tl(dup_const_tl(MO_8, 0x7f)); >> >> /* set high-bit for non-zero bytes */ >> tcg_gen_and_tl(tmp, source1, constant); >> tcg_gen_add_tl(tmp, tmp, constant); >> tcg_gen_or_tl(tmp, tmp, source1); >> /* extract high-bit to low-bit, for each word */ >> tcg_gen_andc_tl(tmp, tmp, constant); >> tcg_gen_shri_tl(tmp, tmp, 7); >> >> /* Replicate the lsb of each byte across the byte. */ >> tcg_gen_muli_tl(ret, tmp, 0xff); >> >> tcg_temp_free(tmp); >> } >> ``` >> >> It does pass my own test sequences. > > I am running it against SPEC at the moment, using optimized > strlen/strcpy/strcmp functions using orc.b. > The verdict on that should be available later today... off topic but relates, for Zb (and similar things in the future) whats the strategy for change management/discovery. I understand you can hardcode things for quick test, but for a proper glibc implementation this would be an IFUNC but there seems to be no architectural way per spec (for software/kernel) to discover this. Same issue is with building linux kernel with Zb - how do we make sure that hardware/sim supports Zb when running corresponding software. It seems some generic discovery/enumeration scheme is in works but what to do in the interim. Thx, -Vineet