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Tue, 1 Jun 2021 14:24:28 +0000 Subject: Re: [PATCH v4 2/3] clocksource: Rewrite Xilinx AXI timer driver To: Lee Jones Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, michal.simek@xilinx.com, linux-kernel@vger.kernel.org, Alvaro Gamez , linux-arm-kernel@lists.infradead.org, Daniel Lezcano , Thomas Gleixner References: <20210528214522.617435-1-sean.anderson@seco.com> <20210528214522.617435-2-sean.anderson@seco.com> <20210601084734.GX543307@dell> From: Sean Anderson Message-ID: Date: Tue, 1 Jun 2021 10:24:23 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 In-Reply-To: <20210601084734.GX543307@dell> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [50.195.82.171] X-ClientProxiedBy: BL1P223CA0010.NAMP223.PROD.OUTLOOK.COM (2603:10b6:208:2c4::15) To DB7PR03MB4523.eurprd03.prod.outlook.com (2603:10a6:10:19::27) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from [172.27.1.65] (50.195.82.171) by BL1P223CA0010.NAMP223.PROD.OUTLOOK.COM (2603:10b6:208:2c4::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4173.20 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: =?utf-8?B?MXZCeUVycXJQc0htWitaM0R0RC8zbkMxcG9YcnhCaDNXNFl0R0pLcWdkbXli?= =?utf-8?B?TFBCbWo2UUhKWjlIZ1dUZEpNSWdOanhNRUxiY3dObTUvREkzUEMwdjkzVE56?= =?utf-8?B?MDRmem9scmFSekVmWUhaOHVmeXgrN1ZRTzJwSjZBbTN6YUVCb1Ruakdhdk9p?= =?utf-8?B?Y3YxV2FnWStYMHQrMlhrZjYvZ2lIeG5SUTY5RlNxN1FPUlVMbThEVks3aWFS?= =?utf-8?B?S0l6WUp0OE1hZzRxYXJ1cVdvUFpUc0VSMVMxK2U3UTBub2NvR250ejNBMWtw?= =?utf-8?B?aHR3ZEhaTU1rbHlvaDVYR2lxRmtrYjN5dTJoQkM3VFJsb2NBN01wYkg3RXds?= =?utf-8?B?RElxSENxb04xMWQxSW05UE9aY0tpdzFpNWIyQytwNXlJdkIzOWNVKzNRY0N2?= =?utf-8?B?VjJ5eDhOYThmNnQ5cnlZeUQ0S3FCUHNFbGFkVDQvMklkZzZnNjBVWlZieXNa?= =?utf-8?B?WndZMmdSWSszRWhiSXRTRy84bytNdlVmbVBFaXF6QXNnS0dHa3E1K2xlS0VT?= =?utf-8?B?QkNDTUx0NFZsd2tGSTZPOVZ1T2o4VVl4b1BDb3k3dy9sNGRYTW1qN0RWTFA0?= =?utf-8?B?cmcvbHRscGhWRHdldGdRRU9WNUFRTjRNeVBXZG1UZDBZOERQb3ZjYXVQRCtM?= =?utf-8?B?N2oyUTlVQVpzb0lQM0tMeENtZGplakdRbitQbEZVTmJuSStJRzJoVWhkdWtN?= =?utf-8?B?NmpBWjdXT0VzR0dBUEh0TGNHWFVsb2tRNmtDTGw2L3Q1K2xjU25GbVJSQzVl?= =?utf-8?B?TnppZXVBNW11R3FpZjQxNjIwVWs4UUtHcCtkQ2V5L0ZKblh2VlNlYkowQnJE?= =?utf-8?B?TUJCNHJ3ZU5XSnl3bEUrMENTZmQvSVBDVXpKVmhEN2JVU0d5ZzBVRmI5TitQ?= =?utf-8?B?a3d6c3d1U1pVdFkyWUF5ekI0V0padDAyNlR2OEk4MmJxb2NMRGZwZTdNOUd0?= =?utf-8?B?Z0FHNXF6Rm1LYTUyZUpkS2ZqN0NwTkVrUGR6aUozUWVEVElqKzFtaklVRVJ6?= =?utf-8?B?aDV0Rk15ZXJEVXRoN1hDbFl3aksrUHJXd3E0SWo5YWxLTDVLNVJkdFVsK24x?= =?utf-8?B?R0JCa2kwdmdPMjc3YUJuNlFUUjFOMUFVRjhPbFNrc25Ld0x0dGpVWXZ6RGlO?= =?utf-8?B?OFR1MlpYVXVTTjFCdFdhVVBFYzFCaTlzM1hzQThnNWVicVpsMlRvN3FpYUIx?= =?utf-8?B?My9HY1NhYVhreFRXYjdyWDNTTkk5ZW1NUXRQNXJMWGtpSlBXTmRmRkpjbi9T?= =?utf-8?B?VkdEVVUvb1ZBNUxWU0NOc1VUdzBFOEdGWWwxTk0rcExjQm5vN0crNnVyd2o1?= =?utf-8?B?Q3JHejFENDVzSCsxeWtOL0MrVHllTmFWSExWUmFhZmI5ZXNuRW1CWm5PNnVi?= =?utf-8?B?ZlVkbnB4dkJLRGZqNXhYd2F3WXFHVWpoTzdNY2MvaVd1SURJbUhMQWRzUmhQ?= =?utf-8?B?RUpKTE5RdytEZXE4bHBwRHBJU1NyTTlGUXdRMlM2VThGMldpb05KUjRvZjBk?= =?utf-8?B?N1hYQTlCNVdRQXhvRXFqNTkwc2VZMlpsZ281bTgxM1d0eFJHU0pKUFhRUjFW?= =?utf-8?B?Nnk3TnlMZ0IyMlJHQjRDWkoxQ21HMG5jVGFKTDFBZDdWb3EvOXJPN3BaUDlR?= =?utf-8?B?MCtRV09Ec3AvS3JRWTdVYVNjcnVraG5JNmpWbXhmdXRSZk5XSXAvdlZzK3ZK?= =?utf-8?B?cnBPWDRvVGFJVmRmVjNDMVg0NytPRmpwVHBSTy82cGl0Y1A4VUZ6VkhLQy9n?= =?utf-8?Q?1cNo5ryVd14zEPmbO+qkAUZkkvaplRerTz4ZK0y?= X-OriginatorOrg: seco.com X-MS-Exchange-CrossTenant-Network-Message-Id: 256cf883-2c4e-4895-6ca3-08d92508f724 X-MS-Exchange-CrossTenant-AuthSource: DB7PR03MB4523.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jun 2021 14:24:28.8010 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: bebe97c3-6438-442e-ade3-ff17aa50e733 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 9BLzHbWjUNjw7Erqjr20u+FvL/BhLfWjqQGOK2P+Cvi2mOoKihOtH3S2JS069z3QjXv+DlBQnlyZNs2QeZWDhQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR03MB6027 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 6/1/21 4:47 AM, Lee Jones wrote: > On Fri, 28 May 2021, Sean Anderson wrote: > >> This rewrites the Xilinx AXI timer driver to be more platform agnostic. >> Some common code has been split off so it can be reused. These routines >> currently live in drivers/mfd. The largest changes have taken place in the >> initialization: >> >> - We now support any number of timer devices, possibly with only one >> counter each. The first counter will be used as a clocksource. Every >> other counter will be used as a clockevent. >> - We do not use timer_of_init because we need to perform some tasks in >> between different stages. For example, we must ensure that ->read and >> ->write are initialized before registering the irq. This can only happen >> after we have gotten the register base (to detect endianness). We also >> have a rather unusual clock initialization sequence in order to remain >> backwards compatible. Due to this, it's ok for the initial clock request >> to fail, and we do not want other initialization to be undone. Lastly, it >> is more convenient to do one allocation for xilinx_clockevent_device than >> to do one for timer_of and one for xilinx_timer_priv. >> - We now pay attention to xlnx,count-width and handle smaller width timers. >> The default remains 32. >> >> Signed-off-by: Sean Anderson >> --- >> This has been tested on microblaze qemu. >> >> Changes in v4: >> - Break out clock* drivers into their own file >> >> arch/microblaze/kernel/Makefile | 3 +- >> arch/microblaze/kernel/timer.c | 326 ----------------------------- >> drivers/clocksource/Kconfig | 11 + >> drivers/clocksource/Makefile | 1 + >> drivers/clocksource/timer-xilinx.c | 300 ++++++++++++++++++++++++++ >> drivers/mfd/Makefile | 4 + >> drivers/mfd/xilinx-timer.c | 147 +++++++++++++ > > I'm confused! > >> include/linux/mfd/xilinx-timer.h | 134 ++++++++++++ >> 8 files changed, 598 insertions(+), 328 deletions(-) >> delete mode 100644 arch/microblaze/kernel/timer.c >> create mode 100644 drivers/clocksource/timer-xilinx.c >> create mode 100644 drivers/mfd/xilinx-timer.c >> create mode 100644 include/linux/mfd/xilinx-timer.h > > [...] > >> +// SPDX-License-Identifier: GPL-2.0+ >> +/* >> + * Copyright (C) 2021 Sean Anderson >> + * >> + * For Xilinx LogiCORE IP AXI Timer documentation, refer to DS764: >> + * https://www.xilinx.com/support/documentation/ip_documentation/axi_timer/v1_03_a/axi_timer_ds764.pdf >> + */ >> + >> +#include >> +#include >> +#include >> +#include > > RED FLAG: You are not using the MFD API here. Should I be? > >> +#define TCSR0 0x00 >> +#define TLR0 0x04 >> +#define TCR0 0x08 >> +#define TCSR1 0x10 >> +#define TLR1 0x14 >> +#define TCR1 0x18 >> + >> +#define TCSR_MDT BIT(0) >> +#define TCSR_UDT BIT(1) >> +#define TCSR_GENT BIT(2) >> +#define TCSR_CAPT BIT(3) >> +#define TCSR_ARHT BIT(4) >> +#define TCSR_LOAD BIT(5) >> +#define TCSR_ENIT BIT(6) >> +#define TCSR_ENT BIT(7) >> +#define TCSR_TINT BIT(8) >> +#define TCSR_PWMA BIT(9) >> +#define TCSR_ENALL BIT(10) >> +#define TCSR_CASC BIT(11) >> + >> +/* readl/writel wrappers to support BE systems */ >> + >> +static u32 xilinx_ioread32be(const void __iomem *addr) >> +{ >> + return ioread32be(addr); >> +} >> + >> +static void xilinx_iowrite32be(u32 value, void __iomem *addr) >> +{ >> + iowrite32be(value, addr); >> +} >> + >> +static u32 xilinx_ioread32(const void __iomem *addr) >> +{ >> + return ioread32(addr); >> +} >> + >> +static void xilinx_iowrite32(u32 value, void __iomem *addr) >> +{ >> + iowrite32(value, addr); >> +} > > Abstraction for the sake of abstraction, is not allowed. > > Just use the io*() calls directly in-place. Can't. The call signatures on some arches have volatile addr and some do not. So without these wrappers, we will get warnings about how the function has the wrong type. > >> +int xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 *tlr, >> + u32 tcsr, u64 cycles) >> +{ >> + if (cycles < 2 || cycles > priv->max + 2) >> + return -ERANGE; >> + >> + if (tcsr & TCSR_UDT) >> + *tlr = cycles - 2; >> + else >> + *tlr = priv->max - cycles + 2; >> + >> + return 0; >> +} >> + >> +int xilinx_timer_tlr_period(struct xilinx_timer_priv *priv, u32 *tlr, >> + u32 tcsr, unsigned int period) >> +{ >> + u64 cycles = DIV_ROUND_DOWN_ULL((u64)period * clk_get_rate(priv->clk), >> + NSEC_PER_SEC); >> + >> + return xilinx_timer_tlr_cycles(priv, tlr, tcsr, cycles); >> +} >> + >> +unsigned int xilinx_timer_get_period(struct xilinx_timer_priv *priv, >> + u32 tlr, u32 tcsr) >> +{ >> + u64 cycles; >> + >> + if (tcsr & TCSR_UDT) >> + cycles = tlr + 2; >> + else >> + cycles = priv->max - tlr + 2; >> + >> + return DIV_ROUND_UP_ULL(cycles * NSEC_PER_SEC, >> + clk_get_rate(priv->clk)); >> +} >> + >> +int xilinx_timer_common_init(struct device_node *np, >> + struct xilinx_timer_priv *priv, >> + u32 *one_timer) >> +{ >> + int ret; >> + u32 tcsr0, width; >> + >> + >> + priv->read = xilinx_ioread32; >> + priv->write = xilinx_iowrite32; >> + /* >> + * If PWM mode is enabled, we should try not to disturb it. Use >> + * CAPT since if PWM mode is enabled then MDT will be set as >> + * well. >> + * >> + * First, clear CAPT and verify that it has been cleared >> + */ >> + tcsr0 = xilinx_timer_read(priv, TCSR0); >> + xilinx_timer_write(priv, tcsr0 & ~(TCSR_CAPT & swab(TCSR_CAPT)), TCSR0); >> + tcsr0 = xilinx_timer_read(priv, TCSR0); >> + if (tcsr0 & (TCSR_CAPT | swab(TCSR_CAPT))) { >> + pr_err("%pOF: cannot determine endianness\n", np); >> + return -EOPNOTSUPP; >> + } >> + >> + /* Then check to make sure our write sticks */ >> + xilinx_timer_write(priv, tcsr0 | TCSR_CAPT, TCSR0); >> + if (!(xilinx_timer_read(priv, TCSR0) & TCSR_CAPT)) { >> + priv->read = xilinx_ioread32be; >> + priv->write = xilinx_iowrite32be; >> + } >> + >> + ret = of_property_read_u32(np, "xlnx,one-timer-only", one_timer); >> + if (ret) { >> + pr_err("%pOF: err %d: xlnx,one-timer-only\n", np, ret); >> + return ret; >> + } else if (*one_timer && *one_timer != 1) { >> + pr_err("%pOF: xlnx,one-timer-only must be 0 or 1\n", np); >> + return -EINVAL; >> + } >> + >> + ret = of_property_read_u32(np, "xlnx,count-width", &width); >> + if (ret == -EINVAL) { >> + width = 32; >> + } else if (ret) { >> + pr_err("%pOF: err %d: xlnx,count-width\n", np, ret); >> + return ret; >> + } else if (width < 8 || width > 32) { >> + pr_err("%pOF: invalid counter width\n", np); >> + return -EINVAL; >> + } >> + priv->max = BIT_ULL(width) - 1; >> + >> + return 0; >> +} > > This is *all* timer stuff. > > What is your rationale for dumping this into MFD? It was requested that common code for the timer and PWM drivers be reused in some way. I stuck it in mfd because I wasn't sure where else to put it. If you have a better location suggestion, I'm all ears --Sean From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBDC3C4708F for ; Tue, 1 Jun 2021 14:26:23 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 96FB7613A9 for ; Tue, 1 Jun 2021 14:26:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 96FB7613A9 Authentication-Results: mail.kernel.org; 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dkim=none (message not signed) header.d=none;linutronix.de; dmarc=none action=none header.from=seco.com; Received: from DB7PR03MB4523.eurprd03.prod.outlook.com (2603:10a6:10:19::27) by DB8PR03MB6027.eurprd03.prod.outlook.com (2603:10a6:10:ec::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4173.21; Tue, 1 Jun 2021 14:24:29 +0000 Received: from DB7PR03MB4523.eurprd03.prod.outlook.com ([fe80::40d5:3554:c709:6b1b]) by DB7PR03MB4523.eurprd03.prod.outlook.com ([fe80::40d5:3554:c709:6b1b%5]) with mapi id 15.20.4173.030; Tue, 1 Jun 2021 14:24:28 +0000 Subject: Re: [PATCH v4 2/3] clocksource: Rewrite Xilinx AXI timer driver To: Lee Jones Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, michal.simek@xilinx.com, linux-kernel@vger.kernel.org, Alvaro Gamez , linux-arm-kernel@lists.infradead.org, Daniel Lezcano , Thomas Gleixner References: <20210528214522.617435-1-sean.anderson@seco.com> <20210528214522.617435-2-sean.anderson@seco.com> <20210601084734.GX543307@dell> From: Sean Anderson Message-ID: Date: Tue, 1 Jun 2021 10:24:23 -0400 User-Agent: Mozilla/5.0 (X11; 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charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 6/1/21 4:47 AM, Lee Jones wrote: > On Fri, 28 May 2021, Sean Anderson wrote: > >> This rewrites the Xilinx AXI timer driver to be more platform agnostic. >> Some common code has been split off so it can be reused. These routines >> currently live in drivers/mfd. The largest changes have taken place in the >> initialization: >> >> - We now support any number of timer devices, possibly with only one >> counter each. The first counter will be used as a clocksource. Every >> other counter will be used as a clockevent. >> - We do not use timer_of_init because we need to perform some tasks in >> between different stages. For example, we must ensure that ->read and >> ->write are initialized before registering the irq. This can only happen >> after we have gotten the register base (to detect endianness). We also >> have a rather unusual clock initialization sequence in order to remain >> backwards compatible. Due to this, it's ok for the initial clock request >> to fail, and we do not want other initialization to be undone. Lastly, it >> is more convenient to do one allocation for xilinx_clockevent_device than >> to do one for timer_of and one for xilinx_timer_priv. >> - We now pay attention to xlnx,count-width and handle smaller width timers. >> The default remains 32. >> >> Signed-off-by: Sean Anderson >> --- >> This has been tested on microblaze qemu. >> >> Changes in v4: >> - Break out clock* drivers into their own file >> >> arch/microblaze/kernel/Makefile | 3 +- >> arch/microblaze/kernel/timer.c | 326 ----------------------------- >> drivers/clocksource/Kconfig | 11 + >> drivers/clocksource/Makefile | 1 + >> drivers/clocksource/timer-xilinx.c | 300 ++++++++++++++++++++++++++ >> drivers/mfd/Makefile | 4 + >> drivers/mfd/xilinx-timer.c | 147 +++++++++++++ > > I'm confused! > >> include/linux/mfd/xilinx-timer.h | 134 ++++++++++++ >> 8 files changed, 598 insertions(+), 328 deletions(-) >> delete mode 100644 arch/microblaze/kernel/timer.c >> create mode 100644 drivers/clocksource/timer-xilinx.c >> create mode 100644 drivers/mfd/xilinx-timer.c >> create mode 100644 include/linux/mfd/xilinx-timer.h > > [...] > >> +// SPDX-License-Identifier: GPL-2.0+ >> +/* >> + * Copyright (C) 2021 Sean Anderson >> + * >> + * For Xilinx LogiCORE IP AXI Timer documentation, refer to DS764: >> + * https://www.xilinx.com/support/documentation/ip_documentation/axi_timer/v1_03_a/axi_timer_ds764.pdf >> + */ >> + >> +#include >> +#include >> +#include >> +#include > > RED FLAG: You are not using the MFD API here. Should I be? > >> +#define TCSR0 0x00 >> +#define TLR0 0x04 >> +#define TCR0 0x08 >> +#define TCSR1 0x10 >> +#define TLR1 0x14 >> +#define TCR1 0x18 >> + >> +#define TCSR_MDT BIT(0) >> +#define TCSR_UDT BIT(1) >> +#define TCSR_GENT BIT(2) >> +#define TCSR_CAPT BIT(3) >> +#define TCSR_ARHT BIT(4) >> +#define TCSR_LOAD BIT(5) >> +#define TCSR_ENIT BIT(6) >> +#define TCSR_ENT BIT(7) >> +#define TCSR_TINT BIT(8) >> +#define TCSR_PWMA BIT(9) >> +#define TCSR_ENALL BIT(10) >> +#define TCSR_CASC BIT(11) >> + >> +/* readl/writel wrappers to support BE systems */ >> + >> +static u32 xilinx_ioread32be(const void __iomem *addr) >> +{ >> + return ioread32be(addr); >> +} >> + >> +static void xilinx_iowrite32be(u32 value, void __iomem *addr) >> +{ >> + iowrite32be(value, addr); >> +} >> + >> +static u32 xilinx_ioread32(const void __iomem *addr) >> +{ >> + return ioread32(addr); >> +} >> + >> +static void xilinx_iowrite32(u32 value, void __iomem *addr) >> +{ >> + iowrite32(value, addr); >> +} > > Abstraction for the sake of abstraction, is not allowed. > > Just use the io*() calls directly in-place. Can't. The call signatures on some arches have volatile addr and some do not. So without these wrappers, we will get warnings about how the function has the wrong type. > >> +int xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 *tlr, >> + u32 tcsr, u64 cycles) >> +{ >> + if (cycles < 2 || cycles > priv->max + 2) >> + return -ERANGE; >> + >> + if (tcsr & TCSR_UDT) >> + *tlr = cycles - 2; >> + else >> + *tlr = priv->max - cycles + 2; >> + >> + return 0; >> +} >> + >> +int xilinx_timer_tlr_period(struct xilinx_timer_priv *priv, u32 *tlr, >> + u32 tcsr, unsigned int period) >> +{ >> + u64 cycles = DIV_ROUND_DOWN_ULL((u64)period * clk_get_rate(priv->clk), >> + NSEC_PER_SEC); >> + >> + return xilinx_timer_tlr_cycles(priv, tlr, tcsr, cycles); >> +} >> + >> +unsigned int xilinx_timer_get_period(struct xilinx_timer_priv *priv, >> + u32 tlr, u32 tcsr) >> +{ >> + u64 cycles; >> + >> + if (tcsr & TCSR_UDT) >> + cycles = tlr + 2; >> + else >> + cycles = priv->max - tlr + 2; >> + >> + return DIV_ROUND_UP_ULL(cycles * NSEC_PER_SEC, >> + clk_get_rate(priv->clk)); >> +} >> + >> +int xilinx_timer_common_init(struct device_node *np, >> + struct xilinx_timer_priv *priv, >> + u32 *one_timer) >> +{ >> + int ret; >> + u32 tcsr0, width; >> + >> + >> + priv->read = xilinx_ioread32; >> + priv->write = xilinx_iowrite32; >> + /* >> + * If PWM mode is enabled, we should try not to disturb it. Use >> + * CAPT since if PWM mode is enabled then MDT will be set as >> + * well. >> + * >> + * First, clear CAPT and verify that it has been cleared >> + */ >> + tcsr0 = xilinx_timer_read(priv, TCSR0); >> + xilinx_timer_write(priv, tcsr0 & ~(TCSR_CAPT & swab(TCSR_CAPT)), TCSR0); >> + tcsr0 = xilinx_timer_read(priv, TCSR0); >> + if (tcsr0 & (TCSR_CAPT | swab(TCSR_CAPT))) { >> + pr_err("%pOF: cannot determine endianness\n", np); >> + return -EOPNOTSUPP; >> + } >> + >> + /* Then check to make sure our write sticks */ >> + xilinx_timer_write(priv, tcsr0 | TCSR_CAPT, TCSR0); >> + if (!(xilinx_timer_read(priv, TCSR0) & TCSR_CAPT)) { >> + priv->read = xilinx_ioread32be; >> + priv->write = xilinx_iowrite32be; >> + } >> + >> + ret = of_property_read_u32(np, "xlnx,one-timer-only", one_timer); >> + if (ret) { >> + pr_err("%pOF: err %d: xlnx,one-timer-only\n", np, ret); >> + return ret; >> + } else if (*one_timer && *one_timer != 1) { >> + pr_err("%pOF: xlnx,one-timer-only must be 0 or 1\n", np); >> + return -EINVAL; >> + } >> + >> + ret = of_property_read_u32(np, "xlnx,count-width", &width); >> + if (ret == -EINVAL) { >> + width = 32; >> + } else if (ret) { >> + pr_err("%pOF: err %d: xlnx,count-width\n", np, ret); >> + return ret; >> + } else if (width < 8 || width > 32) { >> + pr_err("%pOF: invalid counter width\n", np); >> + return -EINVAL; >> + } >> + priv->max = BIT_ULL(width) - 1; >> + >> + return 0; >> +} > > This is *all* timer stuff. > > What is your rationale for dumping this into MFD? It was requested that common code for the timer and PWM drivers be reused in some way. I stuck it in mfd because I wasn't sure where else to put it. If you have a better location suggestion, I'm all ears --Sean _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel