From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD595C3F2D1 for ; Thu, 5 Mar 2020 04:29:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A30922073B for ; Thu, 5 Mar 2020 04:29:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725965AbgCEE3M (ORCPT ); Wed, 4 Mar 2020 23:29:12 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:18834 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725844AbgCEE3M (ORCPT ); Wed, 4 Mar 2020 23:29:12 -0500 Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 0254OG2D136130 for ; Wed, 4 Mar 2020 23:29:11 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2yj3esvx61-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Mar 2020 23:29:10 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 5 Mar 2020 04:29:03 -0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 0254T2l162914792 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 5 Mar 2020 04:29:02 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8694FA405B; Thu, 5 Mar 2020 04:29:02 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 22171A4054; Thu, 5 Mar 2020 04:28:58 +0000 (GMT) Received: from localhost.localdomain (unknown [9.85.82.31]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 5 Mar 2020 04:28:57 +0000 (GMT) Subject: Re: [RFC 00/11] perf: Enhancing perf to export processor hazard information To: Stephane Eranian , Peter Zijlstra Cc: Ravi Bangoria , linuxppc-dev@lists.ozlabs.org, LKML , Michael Ellerman , Paul Mackerras , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Andi Kleen , "Liang, Kan" , Alexey Budankov , yao.jin@linux.intel.com, Robert Richter , "Phillips, Kim" References: <20200302052355.36365-1-ravi.bangoria@linux.ibm.com> <20200302101332.GS18400@hirez.programming.kicks-ass.net> From: maddy Date: Thu, 5 Mar 2020 09:58:57 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-TM-AS-GCONF: 00 x-cbid: 20030504-0016-0000-0000-000002ED4DBE X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20030504-0017-0000-0000-000033509F71 Message-Id: X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.572 definitions=2020-03-04_10:2020-03-04,2020-03-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 mlxscore=0 phishscore=0 spamscore=0 clxscore=1015 suspectscore=0 bulkscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2003050023 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3/3/20 1:51 AM, Stephane Eranian wrote: > On Mon, Mar 2, 2020 at 2:13 AM Peter Zijlstra wrote: >> On Mon, Mar 02, 2020 at 10:53:44AM +0530, Ravi Bangoria wrote: >>> Modern processors export such hazard data in Performance >>> Monitoring Unit (PMU) registers. Ex, 'Sampled Instruction Event >>> Register' on IBM PowerPC[1][2] and 'Instruction-Based Sampling' on >>> AMD[3] provides similar information. >>> >>> Implementation detail: >>> >>> A new sample_type called PERF_SAMPLE_PIPELINE_HAZ is introduced. >>> If it's set, kernel converts arch specific hazard information >>> into generic format: >>> >>> struct perf_pipeline_haz_data { >>> /* Instruction/Opcode type: Load, Store, Branch .... */ >>> __u8 itype; >>> /* Instruction Cache source */ >>> __u8 icache; >>> /* Instruction suffered hazard in pipeline stage */ >>> __u8 hazard_stage; >>> /* Hazard reason */ >>> __u8 hazard_reason; >>> /* Instruction suffered stall in pipeline stage */ >>> __u8 stall_stage; >>> /* Stall reason */ >>> __u8 stall_reason; >>> __u16 pad; >>> }; >> Kim, does this format indeed work for AMD IBS? > > Personally, I don't like the term hazard. This is too IBM Power > specific. We need to find a better term, maybe stall or penalty. Yes, names can be reworked and thinking more on it, how about these as "pipeline" data instead of "hazard" data. > Also worth considering is the support of ARM SPE (Statistical > Profiling Extension) which is their version of IBS. > Whatever gets added need to cover all three with no limitations. Thanks for pointing this out. We looked at the ARM SPE spec and it does provides information like issue latency, translation latency so on. And AMD IBS provides data like fetch latency, tag to retire latency, completion to retire latency and so on when using Fetch sampling.  So yes, will rework the struct definition to include data from ARM SPE and AMD IBS also. Will post out a newer version soon. Thanks for the comments Maddy From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D553FC3F2D1 for ; Thu, 5 Mar 2020 04:31:29 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0F882208CD for ; Thu, 5 Mar 2020 04:31:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0F882208CD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 48XyW23VhDzDqjp for ; Thu, 5 Mar 2020 15:31:26 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=maddy@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 48XyST6KB5zDqht for ; Thu, 5 Mar 2020 15:29:13 +1100 (AEDT) Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 0254OFir136089 for ; Wed, 4 Mar 2020 23:29:11 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2yj3esvx62-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Mar 2020 23:29:10 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 5 Mar 2020 04:29:08 -0000 Received: from b06cxnps3075.portsmouth.uk.ibm.com (9.149.109.195) by e06smtp04.uk.ibm.com (192.168.101.134) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 5 Mar 2020 04:29:03 -0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 0254T2l162914792 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 5 Mar 2020 04:29:02 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8694FA405B; Thu, 5 Mar 2020 04:29:02 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 22171A4054; Thu, 5 Mar 2020 04:28:58 +0000 (GMT) Received: from localhost.localdomain (unknown [9.85.82.31]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 5 Mar 2020 04:28:57 +0000 (GMT) Subject: Re: [RFC 00/11] perf: Enhancing perf to export processor hazard information To: Stephane Eranian , Peter Zijlstra References: <20200302052355.36365-1-ravi.bangoria@linux.ibm.com> <20200302101332.GS18400@hirez.programming.kicks-ass.net> From: maddy Date: Thu, 5 Mar 2020 09:58:57 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-TM-AS-GCONF: 00 x-cbid: 20030504-0016-0000-0000-000002ED4DBE X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20030504-0017-0000-0000-000033509F71 Message-Id: X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-03-04_10:2020-03-04, 2020-03-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 mlxscore=0 phishscore=0 spamscore=0 clxscore=1015 suspectscore=0 bulkscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2003050023 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Ravi Bangoria , Andi Kleen , Alexander Shishkin , Jiri Olsa , LKML , Arnaldo Carvalho de Melo , Adrian Hunter , Robert Richter , yao.jin@linux.intel.com, Ingo Molnar , Paul Mackerras , Namhyung Kim , "Phillips, Kim" , linuxppc-dev@lists.ozlabs.org, Alexey Budankov , "Liang, Kan" Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 3/3/20 1:51 AM, Stephane Eranian wrote: > On Mon, Mar 2, 2020 at 2:13 AM Peter Zijlstra wrote: >> On Mon, Mar 02, 2020 at 10:53:44AM +0530, Ravi Bangoria wrote: >>> Modern processors export such hazard data in Performance >>> Monitoring Unit (PMU) registers. Ex, 'Sampled Instruction Event >>> Register' on IBM PowerPC[1][2] and 'Instruction-Based Sampling' on >>> AMD[3] provides similar information. >>> >>> Implementation detail: >>> >>> A new sample_type called PERF_SAMPLE_PIPELINE_HAZ is introduced. >>> If it's set, kernel converts arch specific hazard information >>> into generic format: >>> >>> struct perf_pipeline_haz_data { >>> /* Instruction/Opcode type: Load, Store, Branch .... */ >>> __u8 itype; >>> /* Instruction Cache source */ >>> __u8 icache; >>> /* Instruction suffered hazard in pipeline stage */ >>> __u8 hazard_stage; >>> /* Hazard reason */ >>> __u8 hazard_reason; >>> /* Instruction suffered stall in pipeline stage */ >>> __u8 stall_stage; >>> /* Stall reason */ >>> __u8 stall_reason; >>> __u16 pad; >>> }; >> Kim, does this format indeed work for AMD IBS? > > Personally, I don't like the term hazard. This is too IBM Power > specific. We need to find a better term, maybe stall or penalty. Yes, names can be reworked and thinking more on it, how about these as "pipeline" data instead of "hazard" data. > Also worth considering is the support of ARM SPE (Statistical > Profiling Extension) which is their version of IBS. > Whatever gets added need to cover all three with no limitations. Thanks for pointing this out. We looked at the ARM SPE spec and it does provides information like issue latency, translation latency so on. And AMD IBS provides data like fetch latency, tag to retire latency, completion to retire latency and so on when using Fetch sampling.  So yes, will rework the struct definition to include data from ARM SPE and AMD IBS also. Will post out a newer version soon. Thanks for the comments Maddy