From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:33059) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hF4CN-00034G-WE for qemu-devel@nongnu.org; Fri, 12 Apr 2019 17:59:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hF4CN-0004ez-0e for qemu-devel@nongnu.org; Fri, 12 Apr 2019 17:59:03 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:40005) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hF4CM-0004eJ-Cc for qemu-devel@nongnu.org; Fri, 12 Apr 2019 17:59:02 -0400 Received: by mail-pg1-x541.google.com with SMTP id d31so5801992pgl.7 for ; Fri, 12 Apr 2019 14:59:02 -0700 (PDT) References: <20190411100836.646-1-david@redhat.com> <20190411100836.646-6-david@redhat.com> From: Richard Henderson Message-ID: Date: Fri, 12 Apr 2019 11:58:56 -1000 MIME-Version: 1.0 In-Reply-To: <20190411100836.646-6-david@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v1 05/41] s390x/tcg: Implement VECTOR ADD WITH CARRY COMPUTE CARRY List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Hildenbrand , qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Cornelia Huck , Thomas Huth , Richard Henderson On 4/11/19 12:08 AM, David Hildenbrand wrote: > +static DisasJumpType op_vaccc(DisasContext *s, DisasOps *o) > +{ > + if (get_field(s->fields, m5) != ES_128) { > + gen_program_exception(s, PGM_SPECIFICATION); > + return DISAS_NORETURN; > + } > + > + gen_gvec_4_ool(get_field(s->fields, v1), get_field(s->fields, v2), > + get_field(s->fields, v3), get_field(s->fields, v4), 0, > + gen_helper_gvec_vaccc128); > + return DISAS_NEXT; > +} An inline expansion could be One possible expansion is tcg_gen_andi_i64(tl, cl, 1); tcg_gen_add2_i64(tl, th, tl, zero, al, zero); tcg_gen_add2_i64(tl, th, tl, th, bl, zero); tcg_gen_add2_i64(tl, th, th, zero, ah, zero); tcg_gen_add2_i64(tl, th, tl, th, bl, zero); /* carry out in th */ This is 8 insns for the addition vs the hw optimal 6, but we're not exactly an optimizing compiler either. ;-) r~