From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A670CCCA47F for ; Tue, 7 Jun 2022 08:12:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238086AbiFGIMU (ORCPT ); Tue, 7 Jun 2022 04:12:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238089AbiFGIMQ (ORCPT ); Tue, 7 Jun 2022 04:12:16 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D0B4C56; Tue, 7 Jun 2022 01:12:11 -0700 (PDT) X-UUID: 8fb8eaf96f42466e8d9402f987ab23a8-20220607 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:8559b49c-3dcb-469a-9da5-0f36edc6332d,OB:0,LO B:20,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,AC TION:release,TS:45 X-CID-INFO: VERSION:1.1.5,REQID:8559b49c-3dcb-469a-9da5-0f36edc6332d,OB:0,LOB: 20,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:45 X-CID-META: VersionHash:2a19b09,CLOUDID:efe1e9e4-2ba2-4dc1-b6c5-11feb6c769e0,C OID:632aa7625d2f,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: 8fb8eaf96f42466e8d9402f987ab23a8-20220607 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1791805342; Tue, 07 Jun 2022 16:12:05 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 7 Jun 2022 16:12:04 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 7 Jun 2022 16:12:04 +0800 Message-ID: Subject: Re: [PATCH v10 18/21] drm/mediatek: Add mt8195 Embedded DisplayPort driver From: CK Hu To: Rex-BC Chen , Guillaume Ranquet , Chun-Kuang Hu , "Philipp Zabel" , David Airlie , "Daniel Vetter" , Rob Herring , "Krzysztof Kozlowski" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , "Kishon Vijay Abraham I" , Vinod Koul , "Helge Deller" , Jitao shi CC: Markus Schneider-Pargmann , , , , , , , Date: Tue, 7 Jun 2022 16:12:04 +0800 In-Reply-To: <20220523104758.29531-19-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> <20220523104758.29531-19-granquet@baylibre.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Rex: On Mon, 2022-05-23 at 12:47 +0200, Guillaume Ranquet wrote: > From: Markus Schneider-Pargmann > > This patch adds a DisplayPort driver for the Mediatek mt8195 SoC. > > It supports the mt8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jason-JH.Lin . > > Signed-off-by: Markus Schneider-Pargmann > Signed-off-by: Guillaume Ranquet > --- [snip] > + > +static int mtk_dp_train_start(struct mtk_dp *mtk_dp) > +{ > + int ret = 0; > + u8 lane_count; > + u8 link_rate; > + u8 train_limit; > + u8 max_link_rate; > + u8 plug_wait; > + > + for (plug_wait = 7; !mtk_dp_plug_state(mtk_dp) && plug_wait > > 0; > + --plug_wait) > + /* Avoid short pulses on the HPD isr */ > + usleep_range(1000, 5000); > + if (plug_wait == 0) { > + mtk_dp->train_state = MTK_DP_TRAIN_STATE_DPIDLE; After return, mtk_dp->train_state would be set to MTK_DP_TRAIN_STATE_DPIDLE, so drop this. > + return -ENODEV; > + } > + > + link_rate = mtk_dp->rx_cap[1]; > + lane_count = mtk_dp->rx_cap[2] & 0x1F; > + > + mtk_dp->train_info.link_rate = min(mtk_dp->max_linkrate, > link_rate); > + mtk_dp->train_info.lane_count = min(mtk_dp->max_lanes, > lane_count); > + link_rate = mtk_dp->train_info.link_rate; > + lane_count = mtk_dp->train_info.lane_count; > + > + switch (link_rate) { > + case MTK_DP_LINKRATE_RBR: > + case MTK_DP_LINKRATE_HBR: > + case MTK_DP_LINKRATE_HBR2: > + case MTK_DP_LINKRATE_HBR25: > + case MTK_DP_LINKRATE_HBR3: > + break; > + default: > + mtk_dp->train_info.link_rate = MTK_DP_LINKRATE_HBR3; > + break; > + }; > + > + max_link_rate = link_rate; > + for (train_limit = 6; train_limit > 0; train_limit--) { > + mtk_dp->train_info.cr_done = false; > + mtk_dp->train_info.eq_done = false; > + > + mtk_dp_train_change_mode(mtk_dp); > + ret = mtk_dp_train_flow(mtk_dp, link_rate, lane_count); > + if (ret) > + return ret; > + > + if (!mtk_dp->train_info.cr_done) { > + switch (link_rate) { > + case MTK_DP_LINKRATE_RBR: > + lane_count = lane_count / 2; > + link_rate = max_link_rate; > + if (lane_count == 0) { > + mtk_dp->train_state = > + MTK_DP_TRAIN_STATE_DPID > LE; After return, mtk_dp->train_state would be set to MTK_DP_TRAIN_STATE_DPIDLE, so drop this. Regards, CK > + return -EIO; > + } > + break; > + case MTK_DP_LINKRATE_HBR: > + link_rate = MTK_DP_LINKRATE_RBR; > + break; > + case MTK_DP_LINKRATE_HBR2: > + link_rate = MTK_DP_LINKRATE_HBR; > + break; > + case MTK_DP_LINKRATE_HBR3: > + link_rate = MTK_DP_LINKRATE_HBR2; > + break; > + default: > + return -EINVAL; > + }; > + } else if (!mtk_dp->train_info.eq_done) { > + if (lane_count == 0) > + return -EIO; > + > + lane_count /= 2; > + } else { > + break; > + } > + } > + > + if (train_limit == 0) > + return -ETIMEDOUT; > + > + return 0; > +} > + From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66D00CCA47C for ; Tue, 7 Jun 2022 08:12:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A764512B02F; Tue, 7 Jun 2022 08:12:12 +0000 (UTC) Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by gabe.freedesktop.org (Postfix) with ESMTPS id 98DD612B02F for ; Tue, 7 Jun 2022 08:12:11 +0000 (UTC) X-UUID: 8fb8eaf96f42466e8d9402f987ab23a8-20220607 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5, REQID:8559b49c-3dcb-469a-9da5-0f36edc6332d, OB:0, LO B:20,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,AC TION:release,TS:45 X-CID-INFO: VERSION:1.1.5, REQID:8559b49c-3dcb-469a-9da5-0f36edc6332d, OB:0, LOB: 20,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:45 X-CID-META: VersionHash:2a19b09, CLOUDID:efe1e9e4-2ba2-4dc1-b6c5-11feb6c769e0, C OID:632aa7625d2f,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: 8fb8eaf96f42466e8d9402f987ab23a8-20220607 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1791805342; Tue, 07 Jun 2022 16:12:05 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 7 Jun 2022 16:12:04 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 7 Jun 2022 16:12:04 +0800 Message-ID: Subject: Re: [PATCH v10 18/21] drm/mediatek: Add mt8195 Embedded DisplayPort driver From: CK Hu To: Rex-BC Chen , Guillaume Ranquet , Chun-Kuang Hu , "Philipp Zabel" , David Airlie , "Daniel Vetter" , Rob Herring , "Krzysztof Kozlowski" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , "Kishon Vijay Abraham I" , Vinod Koul , "Helge Deller" , Jitao shi Date: Tue, 7 Jun 2022 16:12:04 +0800 In-Reply-To: <20220523104758.29531-19-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> <20220523104758.29531-19-granquet@baylibre.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-fbdev@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Markus Schneider-Pargmann , linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi, Rex: On Mon, 2022-05-23 at 12:47 +0200, Guillaume Ranquet wrote: > From: Markus Schneider-Pargmann > > This patch adds a DisplayPort driver for the Mediatek mt8195 SoC. > > It supports the mt8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jason-JH.Lin . > > Signed-off-by: Markus Schneider-Pargmann > Signed-off-by: Guillaume Ranquet > --- [snip] > + > +static int mtk_dp_train_start(struct mtk_dp *mtk_dp) > +{ > + int ret = 0; > + u8 lane_count; > + u8 link_rate; > + u8 train_limit; > + u8 max_link_rate; > + u8 plug_wait; > + > + for (plug_wait = 7; !mtk_dp_plug_state(mtk_dp) && plug_wait > > 0; > + --plug_wait) > + /* Avoid short pulses on the HPD isr */ > + usleep_range(1000, 5000); > + if (plug_wait == 0) { > + mtk_dp->train_state = MTK_DP_TRAIN_STATE_DPIDLE; After return, mtk_dp->train_state would be set to MTK_DP_TRAIN_STATE_DPIDLE, so drop this. > + return -ENODEV; > + } > + > + link_rate = mtk_dp->rx_cap[1]; > + lane_count = mtk_dp->rx_cap[2] & 0x1F; > + > + mtk_dp->train_info.link_rate = min(mtk_dp->max_linkrate, > link_rate); > + mtk_dp->train_info.lane_count = min(mtk_dp->max_lanes, > lane_count); > + link_rate = mtk_dp->train_info.link_rate; > + lane_count = mtk_dp->train_info.lane_count; > + > + switch (link_rate) { > + case MTK_DP_LINKRATE_RBR: > + case MTK_DP_LINKRATE_HBR: > + case MTK_DP_LINKRATE_HBR2: > + case MTK_DP_LINKRATE_HBR25: > + case MTK_DP_LINKRATE_HBR3: > + break; > + default: > + mtk_dp->train_info.link_rate = MTK_DP_LINKRATE_HBR3; > + break; > + }; > + > + max_link_rate = link_rate; > + for (train_limit = 6; train_limit > 0; train_limit--) { > + mtk_dp->train_info.cr_done = false; > + mtk_dp->train_info.eq_done = false; > + > + mtk_dp_train_change_mode(mtk_dp); > + ret = mtk_dp_train_flow(mtk_dp, link_rate, lane_count); > + if (ret) > + return ret; > + > + if (!mtk_dp->train_info.cr_done) { > + switch (link_rate) { > + case MTK_DP_LINKRATE_RBR: > + lane_count = lane_count / 2; > + link_rate = max_link_rate; > + if (lane_count == 0) { > + mtk_dp->train_state = > + MTK_DP_TRAIN_STATE_DPID > LE; After return, mtk_dp->train_state would be set to MTK_DP_TRAIN_STATE_DPIDLE, so drop this. Regards, CK > + return -EIO; > + } > + break; > + case MTK_DP_LINKRATE_HBR: > + link_rate = MTK_DP_LINKRATE_RBR; > + break; > + case MTK_DP_LINKRATE_HBR2: > + link_rate = MTK_DP_LINKRATE_HBR; > + break; > + case MTK_DP_LINKRATE_HBR3: > + link_rate = MTK_DP_LINKRATE_HBR2; > + break; > + default: > + return -EINVAL; > + }; > + } else if (!mtk_dp->train_info.eq_done) { > + if (lane_count == 0) > + return -EIO; > + > + lane_count /= 2; > + } else { > + break; > + } > + } > + > + if (train_limit == 0) > + return -ETIMEDOUT; > + > + return 0; > +} > + From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1047EC433EF for ; Tue, 7 Jun 2022 08:22:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:CC:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=0iWG1IGAWd/M1BwESQngl5jjHiuLBrttOApDIMJZgxo=; b=zloxUg9BjxHmUN kAx0uvRUZ5Vm9TB7ew8L45AjF16wOGMFtPnZ4VeuXQuQutB7MF9EdcVgbYOPJ9VnbD6SkJ2pSGQKM ev3CBvqi4Uo1Sr3PtitM8vIWD4fgRa41ZfrdbxtlqHnK1ljCoBkwNXFtH6LqzvVgO9tPoMJMg5VeN asAJBsJPd0xVbzmTtmhcT3Rc6wWv4SecBqt95LjAaT2RfPMYIHNQKMlVLQCKZ7/iHkkl8H76kBI2I D+VhyFun1fRdSZxvPMDmsQR90ZAUXbilv+3oAL61pNGxA8Z37TVhZ5SHQV3taLXSMoXQKTJ88aeRv gq3vdHEGkU7NY+EE5dYQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nyUTo-005mig-Jb; Tue, 07 Jun 2022 08:22:24 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nyUTe-005mge-6A; Tue, 07 Jun 2022 08:22:15 +0000 X-UUID: cfcd971fb46640b58b3ab39ac5e420c3-20220607 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:ea31bbbe-e0ef-4a9b-8877-04e6432ec7e1,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:2a19b09,CLOUDID:a051eae4-2ba2-4dc1-b6c5-11feb6c769e0,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:0,BEC:nil X-UUID: cfcd971fb46640b58b3ab39ac5e420c3-20220607 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1328904487; Tue, 07 Jun 2022 01:22:08 -0700 Received: from mtkmbs10n2.mediatek.inc (172.21.101.183) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 7 Jun 2022 01:12:05 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 7 Jun 2022 16:12:04 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 7 Jun 2022 16:12:04 +0800 Message-ID: Subject: Re: [PATCH v10 18/21] drm/mediatek: Add mt8195 Embedded DisplayPort driver From: CK Hu To: Rex-BC Chen , Guillaume Ranquet , Chun-Kuang Hu , "Philipp Zabel" , David Airlie , "Daniel Vetter" , Rob Herring , "Krzysztof Kozlowski" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , "Kishon Vijay Abraham I" , Vinod Koul , "Helge Deller" , Jitao shi CC: Markus Schneider-Pargmann , , , , , , , Date: Tue, 7 Jun 2022 16:12:04 +0800 In-Reply-To: <20220523104758.29531-19-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> <20220523104758.29531-19-granquet@baylibre.com> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220607_012214_266517_C12600F5 X-CRM114-Status: GOOD ( 25.78 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi, Rex: On Mon, 2022-05-23 at 12:47 +0200, Guillaume Ranquet wrote: > From: Markus Schneider-Pargmann > > This patch adds a DisplayPort driver for the Mediatek mt8195 SoC. > > It supports the mt8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jason-JH.Lin . > > Signed-off-by: Markus Schneider-Pargmann > Signed-off-by: Guillaume Ranquet > --- [snip] > + > +static int mtk_dp_train_start(struct mtk_dp *mtk_dp) > +{ > + int ret = 0; > + u8 lane_count; > + u8 link_rate; > + u8 train_limit; > + u8 max_link_rate; > + u8 plug_wait; > + > + for (plug_wait = 7; !mtk_dp_plug_state(mtk_dp) && plug_wait > > 0; > + --plug_wait) > + /* Avoid short pulses on the HPD isr */ > + usleep_range(1000, 5000); > + if (plug_wait == 0) { > + mtk_dp->train_state = MTK_DP_TRAIN_STATE_DPIDLE; After return, mtk_dp->train_state would be set to MTK_DP_TRAIN_STATE_DPIDLE, so drop this. > + return -ENODEV; > + } > + > + link_rate = mtk_dp->rx_cap[1]; > + lane_count = mtk_dp->rx_cap[2] & 0x1F; > + > + mtk_dp->train_info.link_rate = min(mtk_dp->max_linkrate, > link_rate); > + mtk_dp->train_info.lane_count = min(mtk_dp->max_lanes, > lane_count); > + link_rate = mtk_dp->train_info.link_rate; > + lane_count = mtk_dp->train_info.lane_count; > + > + switch (link_rate) { > + case MTK_DP_LINKRATE_RBR: > + case MTK_DP_LINKRATE_HBR: > + case MTK_DP_LINKRATE_HBR2: > + case MTK_DP_LINKRATE_HBR25: > + case MTK_DP_LINKRATE_HBR3: > + break; > + default: > + mtk_dp->train_info.link_rate = MTK_DP_LINKRATE_HBR3; > + break; > + }; > + > + max_link_rate = link_rate; > + for (train_limit = 6; train_limit > 0; train_limit--) { > + mtk_dp->train_info.cr_done = false; > + mtk_dp->train_info.eq_done = false; > + > + mtk_dp_train_change_mode(mtk_dp); > + ret = mtk_dp_train_flow(mtk_dp, link_rate, lane_count); > + if (ret) > + return ret; > + > + if (!mtk_dp->train_info.cr_done) { > + switch (link_rate) { > + case MTK_DP_LINKRATE_RBR: > + lane_count = lane_count / 2; > + link_rate = max_link_rate; > + if (lane_count == 0) { > + mtk_dp->train_state = > + MTK_DP_TRAIN_STATE_DPID > LE; After return, mtk_dp->train_state would be set to MTK_DP_TRAIN_STATE_DPIDLE, so drop this. Regards, CK > + return -EIO; > + } > + break; > + case MTK_DP_LINKRATE_HBR: > + link_rate = MTK_DP_LINKRATE_RBR; > + break; > + case MTK_DP_LINKRATE_HBR2: > + link_rate = MTK_DP_LINKRATE_HBR; > + break; > + case MTK_DP_LINKRATE_HBR3: > + link_rate = MTK_DP_LINKRATE_HBR2; > + break; > + default: > + return -EINVAL; > + }; > + } else if (!mtk_dp->train_info.eq_done) { > + if (lane_count == 0) > + return -EIO; > + > + lane_count /= 2; > + } else { > + break; > + } > + } > + > + if (train_limit == 0) > + return -ETIMEDOUT; > + > + return 0; > +} > + _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4708C43334 for ; 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Tue, 7 Jun 2022 01:12:05 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 7 Jun 2022 16:12:04 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 7 Jun 2022 16:12:04 +0800 Message-ID: Subject: Re: [PATCH v10 18/21] drm/mediatek: Add mt8195 Embedded DisplayPort driver From: CK Hu To: Rex-BC Chen , Guillaume Ranquet , Chun-Kuang Hu , "Philipp Zabel" , David Airlie , "Daniel Vetter" , Rob Herring , "Krzysztof Kozlowski" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , "Kishon Vijay Abraham I" , Vinod Koul , "Helge Deller" , Jitao shi CC: Markus Schneider-Pargmann , , , , , , , Date: Tue, 7 Jun 2022 16:12:04 +0800 In-Reply-To: <20220523104758.29531-19-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> <20220523104758.29531-19-granquet@baylibre.com> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220607_012214_266517_C12600F5 X-CRM114-Status: GOOD ( 25.78 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Hi, Rex: On Mon, 2022-05-23 at 12:47 +0200, Guillaume Ranquet wrote: > From: Markus Schneider-Pargmann > > This patch adds a DisplayPort driver for the Mediatek mt8195 SoC. > > It supports the mt8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jason-JH.Lin . > > Signed-off-by: Markus Schneider-Pargmann > Signed-off-by: Guillaume Ranquet > --- [snip] > + > +static int mtk_dp_train_start(struct mtk_dp *mtk_dp) > +{ > + int ret = 0; > + u8 lane_count; > + u8 link_rate; > + u8 train_limit; > + u8 max_link_rate; > + u8 plug_wait; > + > + for (plug_wait = 7; !mtk_dp_plug_state(mtk_dp) && plug_wait > > 0; > + --plug_wait) > + /* Avoid short pulses on the HPD isr */ > + usleep_range(1000, 5000); > + if (plug_wait == 0) { > + mtk_dp->train_state = MTK_DP_TRAIN_STATE_DPIDLE; After return, mtk_dp->train_state would be set to MTK_DP_TRAIN_STATE_DPIDLE, so drop this. > + return -ENODEV; > + } > + > + link_rate = mtk_dp->rx_cap[1]; > + lane_count = mtk_dp->rx_cap[2] & 0x1F; > + > + mtk_dp->train_info.link_rate = min(mtk_dp->max_linkrate, > link_rate); > + mtk_dp->train_info.lane_count = min(mtk_dp->max_lanes, > lane_count); > + link_rate = mtk_dp->train_info.link_rate; > + lane_count = mtk_dp->train_info.lane_count; > + > + switch (link_rate) { > + case MTK_DP_LINKRATE_RBR: > + case MTK_DP_LINKRATE_HBR: > + case MTK_DP_LINKRATE_HBR2: > + case MTK_DP_LINKRATE_HBR25: > + case MTK_DP_LINKRATE_HBR3: > + break; > + default: > + mtk_dp->train_info.link_rate = MTK_DP_LINKRATE_HBR3; > + break; > + }; > + > + max_link_rate = link_rate; > + for (train_limit = 6; train_limit > 0; train_limit--) { > + mtk_dp->train_info.cr_done = false; > + mtk_dp->train_info.eq_done = false; > + > + mtk_dp_train_change_mode(mtk_dp); > + ret = mtk_dp_train_flow(mtk_dp, link_rate, lane_count); > + if (ret) > + return ret; > + > + if (!mtk_dp->train_info.cr_done) { > + switch (link_rate) { > + case MTK_DP_LINKRATE_RBR: > + lane_count = lane_count / 2; > + link_rate = max_link_rate; > + if (lane_count == 0) { > + mtk_dp->train_state = > + MTK_DP_TRAIN_STATE_DPID > LE; After return, mtk_dp->train_state would be set to MTK_DP_TRAIN_STATE_DPIDLE, so drop this. Regards, CK > + return -EIO; > + } > + break; > + case MTK_DP_LINKRATE_HBR: > + link_rate = MTK_DP_LINKRATE_RBR; > + break; > + case MTK_DP_LINKRATE_HBR2: > + link_rate = MTK_DP_LINKRATE_HBR; > + break; > + case MTK_DP_LINKRATE_HBR3: > + link_rate = MTK_DP_LINKRATE_HBR2; > + break; > + default: > + return -EINVAL; > + }; > + } else if (!mtk_dp->train_info.eq_done) { > + if (lane_count == 0) > + return -EIO; > + > + lane_count /= 2; > + } else { > + break; > + } > + } > + > + if (train_limit == 0) > + return -ETIMEDOUT; > + > + return 0; > +} > + -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 20109C433EF for ; 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Tue, 7 Jun 2022 01:12:05 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 7 Jun 2022 16:12:04 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 7 Jun 2022 16:12:04 +0800 Message-ID: Subject: Re: [PATCH v10 18/21] drm/mediatek: Add mt8195 Embedded DisplayPort driver From: CK Hu To: Rex-BC Chen , Guillaume Ranquet , Chun-Kuang Hu , "Philipp Zabel" , David Airlie , "Daniel Vetter" , Rob Herring , "Krzysztof Kozlowski" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , "Kishon Vijay Abraham I" , Vinod Koul , "Helge Deller" , Jitao shi CC: Markus Schneider-Pargmann , , , , , , , Date: Tue, 7 Jun 2022 16:12:04 +0800 In-Reply-To: <20220523104758.29531-19-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> <20220523104758.29531-19-granquet@baylibre.com> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220607_012214_266517_C12600F5 X-CRM114-Status: GOOD ( 25.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Rex: On Mon, 2022-05-23 at 12:47 +0200, Guillaume Ranquet wrote: > From: Markus Schneider-Pargmann > > This patch adds a DisplayPort driver for the Mediatek mt8195 SoC. > > It supports the mt8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jason-JH.Lin . > > Signed-off-by: Markus Schneider-Pargmann > Signed-off-by: Guillaume Ranquet > --- [snip] > + > +static int mtk_dp_train_start(struct mtk_dp *mtk_dp) > +{ > + int ret = 0; > + u8 lane_count; > + u8 link_rate; > + u8 train_limit; > + u8 max_link_rate; > + u8 plug_wait; > + > + for (plug_wait = 7; !mtk_dp_plug_state(mtk_dp) && plug_wait > > 0; > + --plug_wait) > + /* Avoid short pulses on the HPD isr */ > + usleep_range(1000, 5000); > + if (plug_wait == 0) { > + mtk_dp->train_state = MTK_DP_TRAIN_STATE_DPIDLE; After return, mtk_dp->train_state would be set to MTK_DP_TRAIN_STATE_DPIDLE, so drop this. > + return -ENODEV; > + } > + > + link_rate = mtk_dp->rx_cap[1]; > + lane_count = mtk_dp->rx_cap[2] & 0x1F; > + > + mtk_dp->train_info.link_rate = min(mtk_dp->max_linkrate, > link_rate); > + mtk_dp->train_info.lane_count = min(mtk_dp->max_lanes, > lane_count); > + link_rate = mtk_dp->train_info.link_rate; > + lane_count = mtk_dp->train_info.lane_count; > + > + switch (link_rate) { > + case MTK_DP_LINKRATE_RBR: > + case MTK_DP_LINKRATE_HBR: > + case MTK_DP_LINKRATE_HBR2: > + case MTK_DP_LINKRATE_HBR25: > + case MTK_DP_LINKRATE_HBR3: > + break; > + default: > + mtk_dp->train_info.link_rate = MTK_DP_LINKRATE_HBR3; > + break; > + }; > + > + max_link_rate = link_rate; > + for (train_limit = 6; train_limit > 0; train_limit--) { > + mtk_dp->train_info.cr_done = false; > + mtk_dp->train_info.eq_done = false; > + > + mtk_dp_train_change_mode(mtk_dp); > + ret = mtk_dp_train_flow(mtk_dp, link_rate, lane_count); > + if (ret) > + return ret; > + > + if (!mtk_dp->train_info.cr_done) { > + switch (link_rate) { > + case MTK_DP_LINKRATE_RBR: > + lane_count = lane_count / 2; > + link_rate = max_link_rate; > + if (lane_count == 0) { > + mtk_dp->train_state = > + MTK_DP_TRAIN_STATE_DPID > LE; After return, mtk_dp->train_state would be set to MTK_DP_TRAIN_STATE_DPIDLE, so drop this. Regards, CK > + return -EIO; > + } > + break; > + case MTK_DP_LINKRATE_HBR: > + link_rate = MTK_DP_LINKRATE_RBR; > + break; > + case MTK_DP_LINKRATE_HBR2: > + link_rate = MTK_DP_LINKRATE_HBR; > + break; > + case MTK_DP_LINKRATE_HBR3: > + link_rate = MTK_DP_LINKRATE_HBR2; > + break; > + default: > + return -EINVAL; > + }; > + } else if (!mtk_dp->train_info.eq_done) { > + if (lane_count == 0) > + return -EIO; > + > + lane_count /= 2; > + } else { > + break; > + } > + } > + > + if (train_limit == 0) > + return -ETIMEDOUT; > + > + return 0; > +} > + _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel