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Subject: Re: [PATCH V4 0/4] powerpc/perf: Add support for perf extended regs
 in powerpc
To: Athira Rajeev <atrajeev@linux.vnet.ibm.com>, mpe@ellerman.id.au
References: <1595774713-1482-1-git-send-email-atrajeev@linux.vnet.ibm.com>
From: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
Message-ID: <ff9affcd-aea1-b77c-0d96-245bdb774adb@linux.ibm.com>
Date: Mon, 27 Jul 2020 12:33:40 +0530
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Cc: Ravi Bangoria <ravi.bangoria@linux.ibm.com>, mikey@neuling.org,
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On 7/26/20 8:15 PM, Athira Rajeev wrote:
> Patch set to add support for perf extended register capability in
> powerpc. The capability flag PERF_PMU_CAP_EXTENDED_REGS, is used to
> indicate the PMU which support extended registers. The generic code
> define the mask of extended registers as 0 for non supported architectures.
> 
> Patches 1 and 2 are the kernel side changes needed to include
> base support for extended regs in powerpc and in power10.
> Patches 3 and 4 are the perf tools side changes needed to support the
> extended registers.
> 
> patch 1/4 defines the PERF_PMU_CAP_EXTENDED_REGS mask to output the
> values of mmcr0,mmcr1,mmcr2 for POWER9. Defines `PERF_REG_EXTENDED_MASK`
> at runtime which contains mask value of the supported registers under
> extended regs.
> 
> patch 2/4 adds the extended regs support for power10 and exposes
> MMCR3, SIER2, SIER3 registers as part of extended regs.
> 
> Patch 3/4 and 4/4 adds extended regs to sample_reg_mask in the tool
> side to use with `-I?` option for power9 and power10 respectively.
> 
> Ravi bangoria found an issue with `perf record -I` while testing the
> changes. The same issue is currently being worked on here:
> https://lkml.org/lkml/2020/7/19/413 and will be resolved once fix
> from Jin Yao is merged.
> 
> This patch series is based on powerpc/next

Apart from the issue with patch #1, the series LGTM..

Reviewed-and-Tested-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com>