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[62.143.94.109]) by smtp.gmail.com with ESMTPSA id my44-20020a1709065a6c00b006f3ef214de4sm7747900ejc.74.2022.05.25.08.58.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 25 May 2022 08:58:59 -0700 (PDT) Message-ID: Date: Wed, 25 May 2022 17:58:58 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.0 Subject: Re: [PATCH 3/5] riscv: smp: Support for 64bit hartid Content-Language: en-US To: Sunil V L Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L , Palmer Dabbelt , Daniel Lezcano , Ard Biesheuvel , Atish Patra , Anup Patel , Thomas Gleixner , Albert Ou , Paul Walmsley , Marc Zyngier References: <20220525151106.2176147-1-sunilvl@ventanamicro.com> <20220525151106.2176147-4-sunilvl@ventanamicro.com> From: Heinrich Schuchardt In-Reply-To: <20220525151106.2176147-4-sunilvl@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/25/22 17:11, Sunil V L wrote: > The hartid can be a 64bit value on RV64 platforms. This patch > modifies the hartid parameter in riscv_hartid_to_cpuid() as > unsigned long so that it can hold 64bit value on RV64 platforms. > > Signed-off-by: Sunil V L Reviewed-by: Heinrich Schuchardt > --- > arch/riscv/include/asm/smp.h | 4 ++-- > arch/riscv/kernel/smp.c | 4 ++-- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h > index 23170c933d73..d3443be7eedc 100644 > --- a/arch/riscv/include/asm/smp.h > +++ b/arch/riscv/include/asm/smp.h > @@ -42,7 +42,7 @@ void arch_send_call_function_ipi_mask(struct cpumask *mask); > /* Hook for the generic smp_call_function_single() routine. */ > void arch_send_call_function_single_ipi(int cpu); > > -int riscv_hartid_to_cpuid(int hartid); > +int riscv_hartid_to_cpuid(unsigned long hartid); > > /* Set custom IPI operations */ > void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops); > @@ -70,7 +70,7 @@ static inline void show_ipi_stats(struct seq_file *p, int prec) > { > } > > -static inline int riscv_hartid_to_cpuid(int hartid) > +static inline int riscv_hartid_to_cpuid(unsigned long hartid) > { > if (hartid == boot_cpu_hartid) > return 0; > diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c > index b5d30ea92292..018e7dc45df6 100644 > --- a/arch/riscv/kernel/smp.c > +++ b/arch/riscv/kernel/smp.c > @@ -47,7 +47,7 @@ static struct { > unsigned long bits ____cacheline_aligned; > } ipi_data[NR_CPUS] __cacheline_aligned; > > -int riscv_hartid_to_cpuid(int hartid) > +int riscv_hartid_to_cpuid(unsigned long hartid) > { > int i; > > @@ -55,7 +55,7 @@ int riscv_hartid_to_cpuid(int hartid) > if (cpuid_to_hartid_map(i) == hartid) > return i; > > - pr_err("Couldn't find cpu id for hartid [%d]\n", hartid); > + pr_err("Couldn't find cpu id for hartid [%lu]\n", hartid); > return -ENOENT; > } > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 061AEC433F5 for ; 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[62.143.94.109]) by smtp.gmail.com with ESMTPSA id my44-20020a1709065a6c00b006f3ef214de4sm7747900ejc.74.2022.05.25.08.58.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 25 May 2022 08:58:59 -0700 (PDT) Message-ID: Date: Wed, 25 May 2022 17:58:58 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.0 Subject: Re: [PATCH 3/5] riscv: smp: Support for 64bit hartid Content-Language: en-US To: Sunil V L Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L , Palmer Dabbelt , Daniel Lezcano , Ard Biesheuvel , Atish Patra , Anup Patel , Thomas Gleixner , Albert Ou , Paul Walmsley , Marc Zyngier References: <20220525151106.2176147-1-sunilvl@ventanamicro.com> <20220525151106.2176147-4-sunilvl@ventanamicro.com> From: Heinrich Schuchardt In-Reply-To: <20220525151106.2176147-4-sunilvl@ventanamicro.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220525_085903_794750_0A1B310C X-CRM114-Status: GOOD ( 18.34 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 5/25/22 17:11, Sunil V L wrote: > The hartid can be a 64bit value on RV64 platforms. This patch > modifies the hartid parameter in riscv_hartid_to_cpuid() as > unsigned long so that it can hold 64bit value on RV64 platforms. > > Signed-off-by: Sunil V L Reviewed-by: Heinrich Schuchardt > --- > arch/riscv/include/asm/smp.h | 4 ++-- > arch/riscv/kernel/smp.c | 4 ++-- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h > index 23170c933d73..d3443be7eedc 100644 > --- a/arch/riscv/include/asm/smp.h > +++ b/arch/riscv/include/asm/smp.h > @@ -42,7 +42,7 @@ void arch_send_call_function_ipi_mask(struct cpumask *mask); > /* Hook for the generic smp_call_function_single() routine. */ > void arch_send_call_function_single_ipi(int cpu); > > -int riscv_hartid_to_cpuid(int hartid); > +int riscv_hartid_to_cpuid(unsigned long hartid); > > /* Set custom IPI operations */ > void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops); > @@ -70,7 +70,7 @@ static inline void show_ipi_stats(struct seq_file *p, int prec) > { > } > > -static inline int riscv_hartid_to_cpuid(int hartid) > +static inline int riscv_hartid_to_cpuid(unsigned long hartid) > { > if (hartid == boot_cpu_hartid) > return 0; > diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c > index b5d30ea92292..018e7dc45df6 100644 > --- a/arch/riscv/kernel/smp.c > +++ b/arch/riscv/kernel/smp.c > @@ -47,7 +47,7 @@ static struct { > unsigned long bits ____cacheline_aligned; > } ipi_data[NR_CPUS] __cacheline_aligned; > > -int riscv_hartid_to_cpuid(int hartid) > +int riscv_hartid_to_cpuid(unsigned long hartid) > { > int i; > > @@ -55,7 +55,7 @@ int riscv_hartid_to_cpuid(int hartid) > if (cpuid_to_hartid_map(i) == hartid) > return i; > > - pr_err("Couldn't find cpu id for hartid [%d]\n", hartid); > + pr_err("Couldn't find cpu id for hartid [%lu]\n", hartid); > return -ENOENT; > } > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv