* [PATCH 0/3] clk: qcom: gcc-msm8939: several small fixes
@ 2022-09-28 14:56 Dmitry Baryshkov
2022-09-28 14:56 ` [PATCH 1/3] dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml Dmitry Baryshkov
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Dmitry Baryshkov @ 2022-09-28 14:56 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Bryan O'Donoghue
Apply several small fixes used for other Qualcomm clock drivers:
- Use ARRAY_SIZE and parent_hws where applicable in gcc-msm8939 driver
- Move gcc-msm8939 schema from gcc-other to gcc-msm8916 to declare the
clocks/clock-names used by this platform.
Dmitry Baryshkov (3):
dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml
clk: qcom: gcc-msm8939: use parent_hws where possible
clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying
num_parents
.../bindings/clock/qcom,gcc-msm8916.yaml | 11 +-
.../bindings/clock/qcom,gcc-other.yaml | 3 -
drivers/clk/qcom/gcc-msm8939.c | 552 +++++++++---------
3 files changed, 284 insertions(+), 282 deletions(-)
--
2.35.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/3] dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml
2022-09-28 14:56 [PATCH 0/3] clk: qcom: gcc-msm8939: several small fixes Dmitry Baryshkov
@ 2022-09-28 14:56 ` Dmitry Baryshkov
2022-09-28 15:05 ` Bryan O'Donoghue
2022-09-28 17:37 ` Krzysztof Kozlowski
2022-09-28 14:56 ` [PATCH 2/3] clk: qcom: gcc-msm8939: use parent_hws where possible Dmitry Baryshkov
` (2 subsequent siblings)
3 siblings, 2 replies; 8+ messages in thread
From: Dmitry Baryshkov @ 2022-09-28 14:56 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Bryan O'Donoghue
The MSM8939 GCC bindings are fully comptible with MSM8916, the clock
controller requires the same parent clocks, move MSM8939 GCC compatible
to qcom,msm8916.yaml
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../devicetree/bindings/clock/qcom,gcc-msm8916.yaml | 11 ++++++++---
.../devicetree/bindings/clock/qcom,gcc-other.yaml | 3 ---
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml
index 564aa764b17b..2ceb1e501ef9 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8916.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Global Clock & Reset Controller Binding for MSM8916
+title: Qualcomm Global Clock & Reset Controller Binding for MSM8916 and MSM8939
maintainers:
- Stephen Boyd <sboyd@kernel.org>
@@ -12,14 +12,19 @@ maintainers:
description: |
Qualcomm global clock control module which supports the clocks, resets and
- power domains on MSM8916.
+ power domains on MSM8916 or MSM8939.
See also:
- dt-bindings/clock/qcom,gcc-msm8916.h
+ - dt-bindings/clock/qcom,gcc-msm8939.h
+ - dt-bindings/reset/qcom,gcc-msm8916.h
+ - dt-bindings/reset/qcom,gcc-msm8939.h
properties:
compatible:
- const: qcom,gcc-msm8916
+ enum:
+ - qcom,gcc-msm8916
+ - qcom,gcc-msm8939
clocks:
items:
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
index aae83a22b5fb..76988e04c7db 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
@@ -18,9 +18,7 @@ description: |
- dt-bindings/clock/qcom,gcc-ipq4019.h
- dt-bindings/clock/qcom,gcc-ipq6018.h
- dt-bindings/reset/qcom,gcc-ipq6018.h
- - dt-bindings/clock/qcom,gcc-msm8939.h
- dt-bindings/clock/qcom,gcc-msm8953.h
- - dt-bindings/reset/qcom,gcc-msm8939.h
- dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
- dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
- dt-bindings/clock/qcom,gcc-mdm9607.h
@@ -38,7 +36,6 @@ properties:
- qcom,gcc-ipq6018
- qcom,gcc-mdm9607
- qcom,gcc-msm8226
- - qcom,gcc-msm8939
- qcom,gcc-msm8953
- qcom,gcc-msm8974
- qcom,gcc-msm8974pro
--
2.35.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/3] clk: qcom: gcc-msm8939: use parent_hws where possible
2022-09-28 14:56 [PATCH 0/3] clk: qcom: gcc-msm8939: several small fixes Dmitry Baryshkov
2022-09-28 14:56 ` [PATCH 1/3] dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml Dmitry Baryshkov
@ 2022-09-28 14:56 ` Dmitry Baryshkov
2022-09-28 14:56 ` [PATCH 3/3] clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
2022-09-29 16:45 ` (subset) [PATCH 0/3] clk: qcom: gcc-msm8939: several small fixes Bjorn Andersson
3 siblings, 0 replies; 8+ messages in thread
From: Dmitry Baryshkov @ 2022-09-28 14:56 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Bryan O'Donoghue
Use parent_hws instead of hanving parent_data with just a single .hw
entry to speed up and simplify parent lookups.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-msm8939.c | 432 ++++++++++++++++-----------------
1 file changed, 216 insertions(+), 216 deletions(-)
diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c
index 8e2d9fb98ad5..9d4f35716990 100644
--- a/drivers/clk/qcom/gcc-msm8939.c
+++ b/drivers/clk/qcom/gcc-msm8939.c
@@ -1568,8 +1568,8 @@ static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_ahbfabric_ixfabric_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &ultaudio_ahbfabric_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &ultaudio_ahbfabric_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1585,8 +1585,8 @@ static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &ultaudio_ahbfabric_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &ultaudio_ahbfabric_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1647,8 +1647,8 @@ static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_lpaif_pri_i2s_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &ultaudio_lpaif_pri_i2s_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &ultaudio_lpaif_pri_i2s_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1678,8 +1678,8 @@ static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_lpaif_sec_i2s_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &ultaudio_lpaif_sec_i2s_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &ultaudio_lpaif_sec_i2s_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1709,8 +1709,8 @@ static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_lpaif_aux_i2s_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &ultaudio_lpaif_aux_i2s_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &ultaudio_lpaif_aux_i2s_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1744,8 +1744,8 @@ static struct clk_branch gcc_ultaudio_avsync_xo_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_avsync_xo_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &ultaudio_xo_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &ultaudio_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1761,8 +1761,8 @@ static struct clk_branch gcc_ultaudio_stc_xo_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_stc_xo_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &ultaudio_xo_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &ultaudio_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1800,8 +1800,8 @@ static struct clk_branch gcc_codec_digcodec_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_codec_digcodec_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &codec_digcodec_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &codec_digcodec_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1817,8 +1817,8 @@ static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_pcnoc_mport_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1833,8 +1833,8 @@ static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_pcnoc_sway_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1871,8 +1871,8 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1899,8 +1899,8 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1916,8 +1916,8 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &blsp1_qup1_spi_apps_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1933,8 +1933,8 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1950,8 +1950,8 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &blsp1_qup2_spi_apps_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1967,8 +1967,8 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1984,8 +1984,8 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &blsp1_qup3_spi_apps_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2001,8 +2001,8 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2018,8 +2018,8 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &blsp1_qup4_spi_apps_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2035,8 +2035,8 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_i2c_apps_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2052,8 +2052,8 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_spi_apps_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &blsp1_qup5_spi_apps_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup5_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2069,8 +2069,8 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_i2c_apps_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2086,8 +2086,8 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_spi_apps_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &blsp1_qup6_spi_apps_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup6_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2103,8 +2103,8 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &blsp1_uart1_apps_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2120,8 +2120,8 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &blsp1_uart2_apps_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2138,8 +2138,8 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2154,8 +2154,8 @@ static struct clk_branch gcc_camss_cci_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &camss_ahb_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2171,8 +2171,8 @@ static struct clk_branch gcc_camss_cci_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &cci_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &cci_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2188,8 +2188,8 @@ static struct clk_branch gcc_camss_csi0_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &camss_ahb_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2205,8 +2205,8 @@ static struct clk_branch gcc_camss_csi0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &csi0_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2222,8 +2222,8 @@ static struct clk_branch gcc_camss_csi0phy_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0phy_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &csi0_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2239,8 +2239,8 @@ static struct clk_branch gcc_camss_csi0pix_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0pix_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &csi0_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2256,8 +2256,8 @@ static struct clk_branch gcc_camss_csi0rdi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0rdi_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &csi0_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2273,8 +2273,8 @@ static struct clk_branch gcc_camss_csi1_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &camss_ahb_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2290,8 +2290,8 @@ static struct clk_branch gcc_camss_csi1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &csi1_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2307,8 +2307,8 @@ static struct clk_branch gcc_camss_csi1phy_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1phy_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &csi1_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2324,8 +2324,8 @@ static struct clk_branch gcc_camss_csi1pix_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1pix_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &csi1_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2341,8 +2341,8 @@ static struct clk_branch gcc_camss_csi1rdi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1rdi_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &csi1_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2358,8 +2358,8 @@ static struct clk_branch gcc_camss_csi_vfe0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi_vfe0_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &vfe0_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &vfe0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2375,8 +2375,8 @@ static struct clk_branch gcc_camss_gp0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_gp0_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &camss_gp0_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_gp0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2392,8 +2392,8 @@ static struct clk_branch gcc_camss_gp1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_gp1_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &camss_gp1_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2409,8 +2409,8 @@ static struct clk_branch gcc_camss_ispif_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ispif_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &camss_ahb_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2426,8 +2426,8 @@ static struct clk_branch gcc_camss_jpeg0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_jpeg0_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &jpeg0_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &jpeg0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2443,8 +2443,8 @@ static struct clk_branch gcc_camss_jpeg_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_jpeg_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &camss_ahb_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2460,8 +2460,8 @@ static struct clk_branch gcc_camss_jpeg_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_jpeg_axi_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &system_mm_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2477,8 +2477,8 @@ static struct clk_branch gcc_camss_mclk0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk0_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &mclk0_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2494,8 +2494,8 @@ static struct clk_branch gcc_camss_mclk1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk1_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &mclk1_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2511,8 +2511,8 @@ static struct clk_branch gcc_camss_micro_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_micro_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &camss_ahb_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2528,8 +2528,8 @@ static struct clk_branch gcc_camss_csi0phytimer_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0phytimer_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &csi0phytimer_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &csi0phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2545,8 +2545,8 @@ static struct clk_branch gcc_camss_csi1phytimer_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1phytimer_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &csi1phytimer_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &csi1phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2562,8 +2562,8 @@ static struct clk_branch gcc_camss_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &camss_ahb_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2579,8 +2579,8 @@ static struct clk_branch gcc_camss_top_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_top_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2596,8 +2596,8 @@ static struct clk_branch gcc_camss_cpp_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cpp_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &camss_ahb_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2613,8 +2613,8 @@ static struct clk_branch gcc_camss_cpp_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cpp_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &cpp_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &cpp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2630,8 +2630,8 @@ static struct clk_branch gcc_camss_vfe0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe0_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &vfe0_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &vfe0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2647,8 +2647,8 @@ static struct clk_branch gcc_camss_vfe_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &camss_ahb_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2664,8 +2664,8 @@ static struct clk_branch gcc_camss_vfe_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe_axi_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &system_mm_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2682,8 +2682,8 @@ static struct clk_branch gcc_crypto_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2700,8 +2700,8 @@ static struct clk_branch gcc_crypto_axi_clk = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_axi_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2718,8 +2718,8 @@ static struct clk_branch gcc_crypto_clk = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &crypto_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &crypto_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2735,8 +2735,8 @@ static struct clk_branch gcc_oxili_gmem_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_oxili_gmem_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &gfx3d_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2752,8 +2752,8 @@ static struct clk_branch gcc_gp1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &gp1_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2769,8 +2769,8 @@ static struct clk_branch gcc_gp2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &gp2_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2786,8 +2786,8 @@ static struct clk_branch gcc_gp3_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &gp3_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2803,8 +2803,8 @@ static struct clk_branch gcc_mdss_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2820,8 +2820,8 @@ static struct clk_branch gcc_mdss_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_axi_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &system_mm_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2837,8 +2837,8 @@ static struct clk_branch gcc_mdss_byte0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_byte0_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &byte0_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2854,8 +2854,8 @@ static struct clk_branch gcc_mdss_byte1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_byte1_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &byte1_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &byte1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2871,8 +2871,8 @@ static struct clk_branch gcc_mdss_esc0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_esc0_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &esc0_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2888,8 +2888,8 @@ static struct clk_branch gcc_mdss_esc1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_esc1_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &esc1_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &esc1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2905,8 +2905,8 @@ static struct clk_branch gcc_mdss_mdp_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_mdp_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &mdp_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2922,8 +2922,8 @@ static struct clk_branch gcc_mdss_pclk0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_pclk0_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pclk0_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2939,8 +2939,8 @@ static struct clk_branch gcc_mdss_pclk1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_pclk1_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pclk1_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2956,8 +2956,8 @@ static struct clk_branch gcc_mdss_vsync_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_vsync_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &vsync_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2973,8 +2973,8 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_cfg_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2990,8 +2990,8 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_q6_bimc_axi_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &bimc_ddr_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &bimc_ddr_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3007,8 +3007,8 @@ static struct clk_branch gcc_oxili_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_oxili_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3024,8 +3024,8 @@ static struct clk_branch gcc_oxili_gfx3d_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_oxili_gfx3d_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &gfx3d_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3041,8 +3041,8 @@ static struct clk_branch gcc_pdm2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pdm2_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3058,8 +3058,8 @@ static struct clk_branch gcc_pdm_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3076,8 +3076,8 @@ static struct clk_branch gcc_prng_ahb_clk = {
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -3092,8 +3092,8 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3109,8 +3109,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &sdcc1_apps_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3126,8 +3126,8 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3143,8 +3143,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &sdcc2_apps_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3161,8 +3161,8 @@ static struct clk_branch gcc_apss_tcu_clk = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_apss_tcu_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &bimc_ddr_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &bimc_ddr_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -3178,8 +3178,8 @@ static struct clk_branch gcc_gfx_tcu_clk = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_gfx_tcu_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &bimc_ddr_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &bimc_ddr_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -3195,8 +3195,8 @@ static struct clk_branch gcc_gfx_tbu_clk = {
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_gfx_tbu_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &bimc_ddr_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &bimc_ddr_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -3212,8 +3212,8 @@ static struct clk_branch gcc_mdp_tbu_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdp_tbu_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &system_mm_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3230,8 +3230,8 @@ static struct clk_branch gcc_venus_tbu_clk = {
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus_tbu_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &system_mm_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3248,8 +3248,8 @@ static struct clk_branch gcc_vfe_tbu_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_vfe_tbu_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &system_mm_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3266,8 +3266,8 @@ static struct clk_branch gcc_jpeg_tbu_clk = {
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_jpeg_tbu_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &system_mm_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3284,8 +3284,8 @@ static struct clk_branch gcc_smmu_cfg_clk = {
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_smmu_cfg_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3302,8 +3302,8 @@ static struct clk_branch gcc_gtcu_ahb_clk = {
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_gtcu_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3320,8 +3320,8 @@ static struct clk_branch gcc_cpp_tbu_clk = {
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpp_tbu_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3338,8 +3338,8 @@ static struct clk_branch gcc_mdp_rt_tbu_clk = {
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdp_rt_tbu_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3355,8 +3355,8 @@ static struct clk_branch gcc_bimc_gfx_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_gfx_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &bimc_gpu_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &bimc_gpu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3372,8 +3372,8 @@ static struct clk_branch gcc_bimc_gpu_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_gpu_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &bimc_gpu_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &bimc_gpu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3401,8 +3401,8 @@ static struct clk_branch gcc_usb_fs_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_fs_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3418,8 +3418,8 @@ static struct clk_branch gcc_usb_fs_ic_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_fs_ic_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &usb_fs_ic_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &usb_fs_ic_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3435,8 +3435,8 @@ static struct clk_branch gcc_usb_fs_system_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_fs_system_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &usb_fs_system_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &usb_fs_system_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3452,8 +3452,8 @@ static struct clk_branch gcc_usb_hs_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3469,8 +3469,8 @@ static struct clk_branch gcc_usb_hs_system_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_system_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &usb_hs_system_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &usb_hs_system_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3486,8 +3486,8 @@ static struct clk_branch gcc_venus0_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus0_ahb_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3503,8 +3503,8 @@ static struct clk_branch gcc_venus0_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus0_axi_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &system_mm_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3520,8 +3520,8 @@ static struct clk_branch gcc_venus0_vcodec0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus0_vcodec0_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &vcodec0_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &vcodec0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3537,8 +3537,8 @@ static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus0_core0_vcodec0_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &vcodec0_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &vcodec0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3554,8 +3554,8 @@ static struct clk_branch gcc_venus0_core1_vcodec0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus0_core1_vcodec0_clk",
- .parent_data = &(const struct clk_parent_data){
- .hw = &vcodec0_clk_src.clkr.hw,
+ .parent_hws = (const struct clk_hw*[]){
+ &vcodec0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
--
2.35.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/3] clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parents
2022-09-28 14:56 [PATCH 0/3] clk: qcom: gcc-msm8939: several small fixes Dmitry Baryshkov
2022-09-28 14:56 ` [PATCH 1/3] dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml Dmitry Baryshkov
2022-09-28 14:56 ` [PATCH 2/3] clk: qcom: gcc-msm8939: use parent_hws where possible Dmitry Baryshkov
@ 2022-09-28 14:56 ` Dmitry Baryshkov
2022-09-28 15:02 ` Bryan O'Donoghue
2022-09-29 16:45 ` (subset) [PATCH 0/3] clk: qcom: gcc-msm8939: several small fixes Bjorn Andersson
3 siblings, 1 reply; 8+ messages in thread
From: Dmitry Baryshkov @ 2022-09-28 14:56 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Bryan O'Donoghue
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-msm8939.c | 120 ++++++++++++++++-----------------
1 file changed, 60 insertions(+), 60 deletions(-)
diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c
index 9d4f35716990..af608f165896 100644
--- a/drivers/clk/qcom/gcc-msm8939.c
+++ b/drivers/clk/qcom/gcc-msm8939.c
@@ -614,7 +614,7 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "pcnoc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -626,7 +626,7 @@ static struct clk_rcg2 system_noc_bfdcd_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "system_noc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_gpll6a_parent_data,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6a_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -638,7 +638,7 @@ static struct clk_rcg2 bimc_ddr_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "bimc_ddr_clk_src",
.parent_data = gcc_xo_gpll0_bimc_parent_data,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc_parent_data),
.ops = &clk_rcg2_ops,
.flags = CLK_GET_RATE_NOCACHE,
},
@@ -651,7 +651,7 @@ static struct clk_rcg2 system_mm_noc_bfdcd_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "system_mm_noc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_gpll6a_parent_data,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6a_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -671,7 +671,7 @@ static struct clk_rcg2 camss_ahb_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_ahb_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -692,7 +692,7 @@ static struct clk_rcg2 apss_ahb_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "apss_ahb_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -711,7 +711,7 @@ static struct clk_rcg2 csi0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -724,7 +724,7 @@ static struct clk_rcg2 csi1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -753,7 +753,7 @@ static struct clk_rcg2 gfx3d_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk_src",
.parent_data = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -782,7 +782,7 @@ static struct clk_rcg2 vfe0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe0_clk_src",
.parent_data = gcc_xo_gpll0_gpll2_gpll4_parent_data,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -801,7 +801,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -826,7 +826,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -839,7 +839,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -853,7 +853,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -866,7 +866,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -880,7 +880,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -893,7 +893,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -907,7 +907,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -920,7 +920,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -934,7 +934,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -947,7 +947,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -961,7 +961,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -994,7 +994,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1008,7 +1008,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1028,7 +1028,7 @@ static struct clk_rcg2 cci_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cci_clk_src",
.parent_data = gcc_xo_gpll0a_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1048,7 +1048,7 @@ static struct clk_rcg2 camss_gp0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp0_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1062,7 +1062,7 @@ static struct clk_rcg2 camss_gp1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp1_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1082,7 +1082,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg0_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1102,7 +1102,7 @@ static struct clk_rcg2 mclk0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk0_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1116,7 +1116,7 @@ static struct clk_rcg2 mclk1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk1_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1135,7 +1135,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0phytimer_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_parent_data,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1148,7 +1148,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1phytimer_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_parent_data,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1171,7 +1171,7 @@ static struct clk_rcg2 cpp_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cpp_clk_src",
.parent_data = gcc_xo_gpll0_gpll2_parent_data,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1193,7 +1193,7 @@ static struct clk_rcg2 crypto_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "crypto_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1212,7 +1212,7 @@ static struct clk_rcg2 gp1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1226,7 +1226,7 @@ static struct clk_rcg2 gp2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1240,7 +1240,7 @@ static struct clk_rcg2 gp3_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1252,7 +1252,7 @@ static struct clk_rcg2 byte0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "byte0_clk_src",
.parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte_parent_data),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -1265,7 +1265,7 @@ static struct clk_rcg2 byte1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "byte1_clk_src",
.parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte_parent_data),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -1284,7 +1284,7 @@ static struct clk_rcg2 esc0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "esc0_clk_src",
.parent_data = gcc_xo_dsibyte_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_dsibyte_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1297,7 +1297,7 @@ static struct clk_rcg2 esc1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "esc1_clk_src",
.parent_data = gcc_xo_dsibyte_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_dsibyte_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1325,7 +1325,7 @@ static struct clk_rcg2 mdp_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "mdp_clk_src",
.parent_data = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1338,7 +1338,7 @@ static struct clk_rcg2 pclk0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk0_clk_src",
.parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy_parent_data),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -1352,7 +1352,7 @@ static struct clk_rcg2 pclk1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk1_clk_src",
.parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy_parent_data),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -1371,7 +1371,7 @@ static struct clk_rcg2 vsync_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "vsync_clk_src",
.parent_data = gcc_xo_gpll0a_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1390,7 +1390,7 @@ static struct clk_rcg2 pdm2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "pdm2_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1416,7 +1416,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_floor_ops,
},
};
@@ -1430,7 +1430,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_floor_ops,
},
};
@@ -1450,7 +1450,7 @@ static struct clk_rcg2 apss_tcu_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "apss_tcu_clk_src",
.parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1473,7 +1473,7 @@ static struct clk_rcg2 bimc_gpu_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "bimc_gpu_clk_src",
.parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data),
.flags = CLK_GET_RATE_NOCACHE,
.ops = &clk_rcg2_ops,
},
@@ -1494,7 +1494,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hs_system_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1512,7 +1512,7 @@ static struct clk_rcg2 usb_fs_system_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_fs_system_clk_src",
.parent_data = gcc_xo_gpll6_gpll0_parent_data,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1530,7 +1530,7 @@ static struct clk_rcg2 usb_fs_ic_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_fs_ic_clk_src",
.parent_data = gcc_xo_gpll6_gpll0a_parent_data,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0a_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1556,7 +1556,7 @@ static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_ahbfabric_clk_src",
.parent_data = gcc_xo_gpll0_gpll1_sleep_parent_data,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1635,7 +1635,7 @@ static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_lpaif_pri_i2s_clk_src",
.parent_data = gcc_xo_gpll1_epi2s_emclk_sleep_parent_data,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll1_epi2s_emclk_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1666,7 +1666,7 @@ static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_lpaif_sec_i2s_clk_src",
.parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1697,7 +1697,7 @@ static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_lpaif_aux_i2s_clk_src",
.parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1732,7 +1732,7 @@ static struct clk_rcg2 ultaudio_xo_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_xo_clk_src",
.parent_data = gcc_xo_sleep_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1788,7 +1788,7 @@ static struct clk_rcg2 codec_digcodec_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "codec_digcodec_clk_src",
.parent_data = gcc_xo_gpll1_emclk_sleep_parent_data,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll1_emclk_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
@@ -1858,7 +1858,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "vcodec0_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
--
2.35.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parents
2022-09-28 14:56 ` [PATCH 3/3] clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
@ 2022-09-28 15:02 ` Bryan O'Donoghue
0 siblings, 0 replies; 8+ messages in thread
From: Bryan O'Donoghue @ 2022-09-28 15:02 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Stephen Boyd, Michael Turquette, Rob Herring,
Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
On 28/09/2022 15:56, Dmitry Baryshkov wrote:
> Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
> adding/removing entries to/from parent_data easy and errorproof.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/clk/qcom/gcc-msm8939.c | 120 ++++++++++++++++-----------------
> 1 file changed, 60 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c
> index 9d4f35716990..af608f165896 100644
> --- a/drivers/clk/qcom/gcc-msm8939.c
> +++ b/drivers/clk/qcom/gcc-msm8939.c
> @@ -614,7 +614,7 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pcnoc_bfdcd_clk_src",
> .parent_data = gcc_xo_gpll0_parent_data,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
> .ops = &clk_rcg2_ops,
> },
> };
Nice
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml
2022-09-28 14:56 ` [PATCH 1/3] dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml Dmitry Baryshkov
@ 2022-09-28 15:05 ` Bryan O'Donoghue
2022-09-28 17:37 ` Krzysztof Kozlowski
1 sibling, 0 replies; 8+ messages in thread
From: Bryan O'Donoghue @ 2022-09-28 15:05 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Stephen Boyd, Michael Turquette, Rob Herring,
Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
On 28/09/2022 15:56, Dmitry Baryshkov wrote:
> The MSM8939 GCC bindings are fully comptible with MSM8916, the clock
> controller requires the same parent clocks, move MSM8939 GCC compatible
> to qcom,msm8916.yaml
I'm not sure they are _all_ the same but definitely agree the two trees
are so close they should live in the same file.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml
2022-09-28 14:56 ` [PATCH 1/3] dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml Dmitry Baryshkov
2022-09-28 15:05 ` Bryan O'Donoghue
@ 2022-09-28 17:37 ` Krzysztof Kozlowski
1 sibling, 0 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-28 17:37 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Stephen Boyd, Michael Turquette, Rob Herring,
Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Bryan O'Donoghue
On 28/09/2022 16:56, Dmitry Baryshkov wrote:
> The MSM8939 GCC bindings are fully comptible with MSM8916, the clock
> controller requires the same parent clocks, move MSM8939 GCC compatible
> to qcom,msm8916.yaml
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../devicetree/bindings/clock/qcom,gcc-msm8916.yaml | 11 ++++++++---
> .../devicetree/bindings/clock/qcom,gcc-other.yaml | 3 ---
> 2 files changed, 8 insertions(+), 6 deletions(-)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: (subset) [PATCH 0/3] clk: qcom: gcc-msm8939: several small fixes
2022-09-28 14:56 [PATCH 0/3] clk: qcom: gcc-msm8939: several small fixes Dmitry Baryshkov
` (2 preceding siblings ...)
2022-09-28 14:56 ` [PATCH 3/3] clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
@ 2022-09-29 16:45 ` Bjorn Andersson
3 siblings, 0 replies; 8+ messages in thread
From: Bjorn Andersson @ 2022-09-29 16:45 UTC (permalink / raw)
To: agross, mturquette, krzysztof.kozlowski+dt, quic_tdas,
konrad.dybcio, sboyd, dmitry.baryshkov, robh+dt
Cc: bryan.odonoghue, linux-clk, linux-arm-msm, devicetree
On Wed, 28 Sep 2022 17:56:06 +0300, Dmitry Baryshkov wrote:
> Apply several small fixes used for other Qualcomm clock drivers:
> - Use ARRAY_SIZE and parent_hws where applicable in gcc-msm8939 driver
> - Move gcc-msm8939 schema from gcc-other to gcc-msm8916 to declare the
> clocks/clock-names used by this platform.
>
> Dmitry Baryshkov (3):
> dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml
> clk: qcom: gcc-msm8939: use parent_hws where possible
> clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying
> num_parents
>
> [...]
Applied, thanks!
[1/3] dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml
commit: 2ab5b5663805ec8e5dc1dbdd9cb14ffac5b06ed1
[2/3] clk: qcom: gcc-msm8939: use parent_hws where possible
commit: f565f9235a675e6eb5a105daa9b70ffa96aab715
[3/3] clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parents
commit: 994c77ed371e464ae4c1bfc316f7aff7309b2d59
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-09-29 16:45 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-28 14:56 [PATCH 0/3] clk: qcom: gcc-msm8939: several small fixes Dmitry Baryshkov
2022-09-28 14:56 ` [PATCH 1/3] dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml Dmitry Baryshkov
2022-09-28 15:05 ` Bryan O'Donoghue
2022-09-28 17:37 ` Krzysztof Kozlowski
2022-09-28 14:56 ` [PATCH 2/3] clk: qcom: gcc-msm8939: use parent_hws where possible Dmitry Baryshkov
2022-09-28 14:56 ` [PATCH 3/3] clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
2022-09-28 15:02 ` Bryan O'Donoghue
2022-09-29 16:45 ` (subset) [PATCH 0/3] clk: qcom: gcc-msm8939: several small fixes Bjorn Andersson
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