From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98872C433E0 for ; Thu, 25 Jun 2020 18:25:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 73BAC20781 for ; Thu, 25 Jun 2020 18:25:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390819AbgFYSZX (ORCPT ); Thu, 25 Jun 2020 14:25:23 -0400 Received: from foss.arm.com ([217.140.110.172]:43054 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390025AbgFYSZW (ORCPT ); Thu, 25 Jun 2020 14:25:22 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 186B1D6E; Thu, 25 Jun 2020 11:25:22 -0700 (PDT) Received: from e113632-lin (e113632-lin.cambridge.arm.com [10.1.194.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6BF923F71E; Thu, 25 Jun 2020 11:25:20 -0700 (PDT) References: <20200624195811.435857-1-maz@kernel.org> <20200624195811.435857-4-maz@kernel.org> User-agent: mu4e 0.9.17; emacs 26.3 From: Valentin Schneider To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Will Deacon , Catalin Marinas , Russell King , Thomas Gleixner , Jason Cooper , Sumit Garg , Florian Fainelli , Gregory Clement , Andrew Lunn , kernel-team@android.com Subject: Re: [PATCH v2 03/17] arm64: Allow IPIs to be handled as normal interrupts In-reply-to: <20200624195811.435857-4-maz@kernel.org> Date: Thu, 25 Jun 2020 19:25:18 +0100 Message-ID: MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 24/06/20 20:57, Marc Zyngier wrote: > @@ -958,9 +958,76 @@ void handle_IPI(int ipinr, struct pt_regs *regs) > > if ((unsigned)ipinr < NR_IPI) > trace_ipi_exit_rcuidle(ipi_types[ipinr]); > +} > + > +/* Legacy version, should go away once all irqchips have been converted */ > +void handle_IPI(int ipinr, struct pt_regs *regs) > +{ > + struct pt_regs *old_regs = set_irq_regs(regs); > + > + irq_enter(); > + do_handle_IPI(ipinr); > + irq_exit(); > + > set_irq_regs(old_regs); > } > > +static irqreturn_t ipi_handler(int irq, void *data) > +{ > + do_handle_IPI(irq - ipi_irq_base); > + return IRQ_HANDLED; > +} > + > +static void ipi_send(const struct cpumask *target, unsigned int ipi) > +{ > + __ipi_send_mask(ipi_desc[ipi], target); > +} > + > +static void ipi_setup(int cpu) > +{ > + if (ipi_irq_base) { > + int i; > + > + for (i = 0; i < nr_ipi; i++) > + enable_percpu_irq(ipi_irq_base + i, 0); > + } > +} Nit: Once we have the irqchip changes in, should we warn & bail out when !ipi_irq_base? Ditto for the teardown > + > +static void ipi_teardown(int cpu) > +{ > + if (ipi_irq_base) { > + int i; > + > + for (i = 0; i < nr_ipi; i++) > + disable_percpu_irq(ipi_irq_base + i); > + } > +} From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3520CC433E0 for ; Fri, 26 Jun 2020 11:35:09 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C8F782082E for ; Fri, 26 Jun 2020 11:35:08 +0000 (UTC) Authentication-Results: mail.kernel.org; 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emacs 26.3 From: Valentin Schneider To: Marc Zyngier Subject: Re: [PATCH v2 03/17] arm64: Allow IPIs to be handled as normal interrupts In-reply-to: <20200624195811.435857-4-maz@kernel.org> Date: Thu, 25 Jun 2020 19:25:18 +0100 Message-ID: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200625_192524_536285_9CB46809 X-CRM114-Status: GOOD ( 14.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sumit Garg , Florian Fainelli , Russell King , Jason Cooper , kernel-team@android.com, Andrew Lunn , Catalin Marinas , Gregory Clement , linux-kernel@vger.kernel.org, Thomas Gleixner , Will Deacon , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 24/06/20 20:57, Marc Zyngier wrote: > @@ -958,9 +958,76 @@ void handle_IPI(int ipinr, struct pt_regs *regs) > > if ((unsigned)ipinr < NR_IPI) > trace_ipi_exit_rcuidle(ipi_types[ipinr]); > +} > + > +/* Legacy version, should go away once all irqchips have been converted */ > +void handle_IPI(int ipinr, struct pt_regs *regs) > +{ > + struct pt_regs *old_regs = set_irq_regs(regs); > + > + irq_enter(); > + do_handle_IPI(ipinr); > + irq_exit(); > + > set_irq_regs(old_regs); > } > > +static irqreturn_t ipi_handler(int irq, void *data) > +{ > + do_handle_IPI(irq - ipi_irq_base); > + return IRQ_HANDLED; > +} > + > +static void ipi_send(const struct cpumask *target, unsigned int ipi) > +{ > + __ipi_send_mask(ipi_desc[ipi], target); > +} > + > +static void ipi_setup(int cpu) > +{ > + if (ipi_irq_base) { > + int i; > + > + for (i = 0; i < nr_ipi; i++) > + enable_percpu_irq(ipi_irq_base + i, 0); > + } > +} Nit: Once we have the irqchip changes in, should we warn & bail out when !ipi_irq_base? Ditto for the teardown > + > +static void ipi_teardown(int cpu) > +{ > + if (ipi_irq_base) { > + int i; > + > + for (i = 0; i < nr_ipi; i++) > + disable_percpu_irq(ipi_irq_base + i); > + } > +} _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel