From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AD76C433E0 for ; Thu, 25 Jun 2020 18:25:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E38D120781 for ; Thu, 25 Jun 2020 18:25:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390770AbgFYSZH (ORCPT ); Thu, 25 Jun 2020 14:25:07 -0400 Received: from foss.arm.com ([217.140.110.172]:43018 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390025AbgFYSZH (ORCPT ); Thu, 25 Jun 2020 14:25:07 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 59F2CD6E; Thu, 25 Jun 2020 11:25:06 -0700 (PDT) Received: from e113632-lin (e113632-lin.cambridge.arm.com [10.1.194.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A3BAE3F71E; Thu, 25 Jun 2020 11:25:04 -0700 (PDT) References: <20200624195811.435857-1-maz@kernel.org> User-agent: mu4e 0.9.17; emacs 26.3 From: Valentin Schneider To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Will Deacon , Catalin Marinas , Russell King , Thomas Gleixner , Jason Cooper , Sumit Garg , Florian Fainelli , Gregory Clement , Andrew Lunn , kernel-team@android.com Subject: Re: [PATCH v2 00/17] arm/arm64: Turning IPIs into normal interrupts In-reply-to: <20200624195811.435857-1-maz@kernel.org> Date: Thu, 25 Jun 2020 19:24:59 +0100 Message-ID: MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Marc, On 24/06/20 20:57, Marc Zyngier wrote: > For as long as SMP ARM has existed, IPIs have been handled as > something special. The arch code and the interrupt controller exchange > a couple of hooks (one to generate an IPI, another to handle it). > > Although this is perfectly manageable, it prevents the use of features > that we could use if IPIs were Linux IRQs (such as pseudo-NMIs). It > also means that each interrupt controller driver has to follow an > architecture-specific interface instead of just implementing the base > irqchip functionalities. The arch code also duplicates a number of > things that the core irq code already does (such as calling > set_irq_regs(), irq_enter()...). > > This series tries to remedy this on arm/arm64 by offering a new > registration interface where the irqchip gives the arch code a range > of interrupts to use for IPIs. The arch code requests these as normal > per-cpu interrupts. > > The bulk of the work is at the interrupt controller level, where all 5 > irqchips used on arm+SMP/arm64 get converted. > > Finally, we drop the legacy registration interface as well as the > custom statistics accounting. > > Note that I have had a look at providing a "generic" interface by > expanding the kernel/irq/ipi.c bag of helpers, but so far all > irqchips have very different requirements, so there is hardly anything > to consolidate for now. Maybe some as hip04 and the Marvell horror get > cleaned up (the latter certainly could do with a good dusting). > > This has been tested on a bunch of 32 and 64bit guests (GICv2, GICv3), > as well as 64bit bare metal (GICv3). The RPi part has only been tested > in QEMU as a 64bit guest, while the HiSi and Marvell parts have only > been compile-tested. > I gave that a spin on Juno r0 and HiKey960 (both GICv2), all good! I also wanted to try it out on my eMAG (to get some GICv3 airtime) but ran into "technical difficulties". I think I'll need to get someone to go poke it (most likely next week). I'm pretty sure I'm the one who should be asking you for hardware, but if there's anything specific you need me to test, please shout. I have a few extra nits/comments in some patches, but it's all fairly minor so FWIW you can also add, for patches [01-10, 14-15]: Reviewed-by: Valentin Schneider I haven't really looked at those other irqchips, but I can give it a shot if no one else shows up. Also I'll most likely look at the arm side, but I'm afraid I'm too well-done right now to pay much more attention to details. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A335C433DF for ; Fri, 26 Jun 2020 11:44:48 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 14C69208B6 for ; Fri, 26 Jun 2020 11:44:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="n9s/HDOH"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="qKInSttA" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 14C69208B6 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:In-reply-to:Subject:To: From:References:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ToalS5raOXnV64CzROewKmc3G0PCMljci1gdiKFN8xc=; b=n9s/HDOHM6OjxC3O6Vi8TDp0N 8qzx/Nvg753yL/LmTXShqtLRhQUf3XydL78E1vuNGEBPJj39xSw0sIeqreIZlXSeB6ZCmBqVJM81m QlvmwAvmKf7gcqrxvfkfmaOUNOfiPUoet0HFKWiFSzWne7sqTY7FIGe5Zn4Kl3u4VHTIa9PIt4sDY hoZFUWk+orkGbqNWdOdY6/li2xOoMhVYW9SgERIrIL2Q41TXR/7lY+L42aPUs+4m246UGlqN1fcsP a4mmBcF+gVWLB8DIv7UEtrK2NV7vsA58jIG2kPHWcrNAH8PCnlaQz+9ozhPfM/uBb252oEBm2UrAZ LoLmGu3ig==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jomlO-0001rH-L5; Fri, 26 Jun 2020 11:43:22 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jolLh-0001xq-J2 for linux-arm-kernel@merlin.infradead.org; Fri, 26 Jun 2020 10:12:45 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Content-Type:MIME-Version:Message-ID: Date:In-reply-to:Subject:Cc:To:From:References:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=a7qr3xwOcCsuhsNVRK0VIZWjVNI7rHAT4PZU1Vqfdhw=; b=qKInSttAVGB/FECmixRIi9a6zF 1ZBMDhr/HMqYylYjva53mFEifsyBQu7GVqDaJrFnLVwUnEjSGCbB/16rtgHhEiVn9XBDAQEbp2Kf9 KwFor3HwedR5L+8D74ejsF0QIfyOxWaYDzNI6H/1TRsZIhUbyRNuS+KRjhx5ekK2w6KEYhbMvZXK8 RtuQn66f5LL6t3wsgV1HF+G64CZLqwhv5dejhKK3joJYUBKsKS7wj+2hAiTfisWBEDNtS6vzcoPNE I1pAkVcj6aXPDmq+6eYnFp7uLA0cuvGPRFSlppwQbHUfPBso1PGVF/QTLrz6LZzRk/2cGp812qoll CLjrSFQQ==; Received: from foss.arm.com ([217.140.110.172]) by casper.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1joWYf-0004e1-QN for linux-arm-kernel@lists.infradead.org; Thu, 25 Jun 2020 18:25:12 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 59F2CD6E; Thu, 25 Jun 2020 11:25:06 -0700 (PDT) Received: from e113632-lin (e113632-lin.cambridge.arm.com [10.1.194.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A3BAE3F71E; Thu, 25 Jun 2020 11:25:04 -0700 (PDT) References: <20200624195811.435857-1-maz@kernel.org> User-agent: mu4e 0.9.17; emacs 26.3 From: Valentin Schneider To: Marc Zyngier Subject: Re: [PATCH v2 00/17] arm/arm64: Turning IPIs into normal interrupts In-reply-to: <20200624195811.435857-1-maz@kernel.org> Date: Thu, 25 Jun 2020 19:24:59 +0100 Message-ID: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200625_192510_119380_CE8D4146 X-CRM114-Status: GOOD ( 25.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sumit Garg , Florian Fainelli , Russell King , Jason Cooper , kernel-team@android.com, Andrew Lunn , Catalin Marinas , Gregory Clement , linux-kernel@vger.kernel.org, Thomas Gleixner , Will Deacon , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, On 24/06/20 20:57, Marc Zyngier wrote: > For as long as SMP ARM has existed, IPIs have been handled as > something special. The arch code and the interrupt controller exchange > a couple of hooks (one to generate an IPI, another to handle it). > > Although this is perfectly manageable, it prevents the use of features > that we could use if IPIs were Linux IRQs (such as pseudo-NMIs). It > also means that each interrupt controller driver has to follow an > architecture-specific interface instead of just implementing the base > irqchip functionalities. The arch code also duplicates a number of > things that the core irq code already does (such as calling > set_irq_regs(), irq_enter()...). > > This series tries to remedy this on arm/arm64 by offering a new > registration interface where the irqchip gives the arch code a range > of interrupts to use for IPIs. The arch code requests these as normal > per-cpu interrupts. > > The bulk of the work is at the interrupt controller level, where all 5 > irqchips used on arm+SMP/arm64 get converted. > > Finally, we drop the legacy registration interface as well as the > custom statistics accounting. > > Note that I have had a look at providing a "generic" interface by > expanding the kernel/irq/ipi.c bag of helpers, but so far all > irqchips have very different requirements, so there is hardly anything > to consolidate for now. Maybe some as hip04 and the Marvell horror get > cleaned up (the latter certainly could do with a good dusting). > > This has been tested on a bunch of 32 and 64bit guests (GICv2, GICv3), > as well as 64bit bare metal (GICv3). The RPi part has only been tested > in QEMU as a 64bit guest, while the HiSi and Marvell parts have only > been compile-tested. > I gave that a spin on Juno r0 and HiKey960 (both GICv2), all good! I also wanted to try it out on my eMAG (to get some GICv3 airtime) but ran into "technical difficulties". I think I'll need to get someone to go poke it (most likely next week). I'm pretty sure I'm the one who should be asking you for hardware, but if there's anything specific you need me to test, please shout. I have a few extra nits/comments in some patches, but it's all fairly minor so FWIW you can also add, for patches [01-10, 14-15]: Reviewed-by: Valentin Schneider I haven't really looked at those other irqchips, but I can give it a shot if no one else shows up. Also I'll most likely look at the arm side, but I'm afraid I'm too well-done right now to pay much more attention to details. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel