From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 347B4C433E2 for ; Wed, 9 Sep 2020 11:34:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0316920897 for ; Wed, 9 Sep 2020 11:34:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729691AbgIILe0 (ORCPT ); Wed, 9 Sep 2020 07:34:26 -0400 Received: from foss.arm.com ([217.140.110.172]:41878 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726883AbgIILaI (ORCPT ); Wed, 9 Sep 2020 07:30:08 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B322B31B; Wed, 9 Sep 2020 04:21:09 -0700 (PDT) Received: from e113632-lin (e113632-lin.cambridge.arm.com [10.1.194.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 627073F68F; Wed, 9 Sep 2020 04:21:08 -0700 (PDT) References: <20200829130016.26106-1-valentin.schneider@arm.com> <678F3D1BB717D949B966B68EAEB446ED482417F4@DGGEMM506-MBX.china.huawei.com> <678F3D1BB717D949B966B68EAEB446ED482431A1@DGGEMM506-MBX.china.huawei.com> User-agent: mu4e 0.9.17; emacs 26.3 From: Valentin Schneider To: "Zengtao \(B\)" Cc: "linux-kernel\@vger.kernel.org" , "linux-arm-kernel\@lists.infradead.org" , Catalin Marinas , Will Deacon , Sudeep Holla , Robin Murphy , Jeremy Linton , Dietmar Eggemann , Morten Rasmussen Subject: Re: [PATCH] arm64: topology: Stop using MPIDR for topology information In-reply-to: <678F3D1BB717D949B966B68EAEB446ED482431A1@DGGEMM506-MBX.china.huawei.com> Date: Wed, 09 Sep 2020 12:21:03 +0100 Message-ID: MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 03/09/20 02:44, B wrote: >> -----Original Message----- >> From: Valentin Schneider [mailto:valentin.schneider@arm.com] >> On 02/09/20 04:24, B wrote: >> > I agree with your idea to remove the topology functionality of MPIDR , >> > but I think we need also consider ARM32 and GIC. >> > >> >> Could you please elaborate? This change doesn't impact arch_topology, so >> only arm64 is affected. > > Yes, this change only affects arm64, my question is that do we need to > leverage it to arm32 since arm32 got the same issue. > > And for GIC we are also using MPIDR for the topology info, but I am sure > It's got the same issue or not, just a suggestion to have a look. So technically yes, we can be bothered by this on arm32 - Sudeep pointed out a list of DT files that shows platforms with non-zero values in Aff1 or above. However, the bigger issue is that artificial separation in clusters of 16 CPUs due to extra limitations on Aff0 (mainly due to GICv3 AIUI). Given that GICv2 can support at most 8 CPU interfaces, I don't think we have it as bad on arm32. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AF5CC433E2 for ; Wed, 9 Sep 2020 11:22:53 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C293321582 for ; Wed, 9 Sep 2020 11:22:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="JrBfO/eV" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C293321582 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:In-reply-to:Subject:To: From:References:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Ra/Z9uwRR8Td0WK9G5ZvBMrVz8aYs0+2OVWHDpeDLKo=; b=JrBfO/eVuFQxbK0dT9xN6AwHK htlYwxe8OdvIldpeYCQlyTVSv9FhouHHC4pZaIfnuLXILJYtre7wysli7d3+jwNISMP613uJQYqMI UQzZlvRLKjGY9PVqf7LC1fo6uiXpVNe/wQd7JbloqFDnT/64Npgy7C++DLZh04mKYNSDMu+oGhVfT 2mBpFuBZaffdT+AHHbhz0Pi1IjDSGylQgbL+QeDfa9BE8OXX/t/B9ATc1Il+QK+8Yb5IveunSPGD3 kzhx8zMMAM4u4UhoIE9euQM3joEglO4JbwRj2B4gDKq0T7qkoeuUb+Hca32nImX4z04mwMJhM+Yxu f+aO1QtNQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFyA7-00059O-V6; Wed, 09 Sep 2020 11:21:16 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFyA4-00058J-Nu for linux-arm-kernel@lists.infradead.org; Wed, 09 Sep 2020 11:21:14 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B322B31B; Wed, 9 Sep 2020 04:21:09 -0700 (PDT) Received: from e113632-lin (e113632-lin.cambridge.arm.com [10.1.194.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 627073F68F; Wed, 9 Sep 2020 04:21:08 -0700 (PDT) References: <20200829130016.26106-1-valentin.schneider@arm.com> <678F3D1BB717D949B966B68EAEB446ED482417F4@DGGEMM506-MBX.china.huawei.com> <678F3D1BB717D949B966B68EAEB446ED482431A1@DGGEMM506-MBX.china.huawei.com> User-agent: mu4e 0.9.17; emacs 26.3 From: Valentin Schneider To: "Zengtao \(B\)" Subject: Re: [PATCH] arm64: topology: Stop using MPIDR for topology information In-reply-to: <678F3D1BB717D949B966B68EAEB446ED482431A1@DGGEMM506-MBX.china.huawei.com> Date: Wed, 09 Sep 2020 12:21:03 +0100 Message-ID: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200909_072112_842281_BA8A4492 X-CRM114-Status: GOOD ( 14.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Will Deacon , Catalin Marinas , "linux-kernel@vger.kernel.org" , Jeremy Linton , Morten Rasmussen , Sudeep Holla , Robin Murphy , Dietmar Eggemann , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 03/09/20 02:44, B wrote: >> -----Original Message----- >> From: Valentin Schneider [mailto:valentin.schneider@arm.com] >> On 02/09/20 04:24, B wrote: >> > I agree with your idea to remove the topology functionality of MPIDR , >> > but I think we need also consider ARM32 and GIC. >> > >> >> Could you please elaborate? This change doesn't impact arch_topology, so >> only arm64 is affected. > > Yes, this change only affects arm64, my question is that do we need to > leverage it to arm32 since arm32 got the same issue. > > And for GIC we are also using MPIDR for the topology info, but I am sure > It's got the same issue or not, just a suggestion to have a look. So technically yes, we can be bothered by this on arm32 - Sudeep pointed out a list of DT files that shows platforms with non-zero values in Aff1 or above. However, the bigger issue is that artificial separation in clusters of 16 CPUs due to extra limitations on Aff0 (mainly due to GICv3 AIUI). Given that GICv2 can support at most 8 CPU interfaces, I don't think we have it as bad on arm32. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel