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Wed, 31 May 2023 10:58:38 -0400 (EDT) Date: Wed, 31 May 2023 15:58:35 +0100 From: Graeme Gregory To: wangyuquan1236@phytium.com.cn Cc: peter.maydell@linaro.org, quic_llindhol@quicinc.com, chenbaozi@phytium.com.cn, qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: Re: [PATCH 1/1] hw/arm/sbsa-ref: use XHCI to replace EHCI Message-ID: References: <20230531070229.334124-1-wangyuquan1236@phytium.com.cn> <20230531070229.334124-2-wangyuquan1236@phytium.com.cn> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230531070229.334124-2-wangyuquan1236@phytium.com.cn> Received-SPF: pass client-ip=64.147.123.25; envelope-from=graeme@xora.org.uk; helo=wout2-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, May 31, 2023 at 03:02:29PM +0800, wangyuquan1236@phytium.com.cn wrote: > From: Yuquan Wang > > The current sbsa-ref cannot use EHCI controller which is only > able to do 32-bit DMA, since sbsa-ref doesn't have RAM above 4GB. > Hence, this uses XHCI to provide a usb controller with 64-bit > DMA capablity instead of EHCI. > Should this be below 4G? Also has EHCI never worked, or has it worked in some modes and so this change should be versioned? Graeme > Signed-off-by: Yuquan Wang > Change-Id: I1376f8bbc0e25dcd9d8a22b6e061cb56b3486394 > --- > hw/arm/sbsa-ref.c | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c > index 792371fdce..f9c0647353 100644 > --- a/hw/arm/sbsa-ref.c > +++ b/hw/arm/sbsa-ref.c > @@ -81,7 +81,7 @@ enum { > SBSA_SECURE_UART_MM, > SBSA_SECURE_MEM, > SBSA_AHCI, > - SBSA_EHCI, > + SBSA_XHCI, > }; > > struct SBSAMachineState { > @@ -118,7 +118,7 @@ static const MemMapEntry sbsa_ref_memmap[] = { > [SBSA_SMMU] = { 0x60050000, 0x00020000 }, > /* Space here reserved for more SMMUs */ > [SBSA_AHCI] = { 0x60100000, 0x00010000 }, > - [SBSA_EHCI] = { 0x60110000, 0x00010000 }, > + [SBSA_XHCI] = { 0x60110000, 0x00010000 }, > /* Space here reserved for other devices */ > [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, > /* 32-bit address PCIE MMIO space */ > @@ -138,7 +138,7 @@ static const int sbsa_ref_irqmap[] = { > [SBSA_SECURE_UART] = 8, > [SBSA_SECURE_UART_MM] = 9, > [SBSA_AHCI] = 10, > - [SBSA_EHCI] = 11, > + [SBSA_XHCI] = 11, > [SBSA_SMMU] = 12, /* ... to 15 */ > [SBSA_GWDT_WS0] = 16, > }; > @@ -558,12 +558,12 @@ static void create_ahci(const SBSAMachineState *sms) > } > } > > -static void create_ehci(const SBSAMachineState *sms) > +static void create_xhci(const SBSAMachineState *sms) > { > - hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base; > - int irq = sbsa_ref_irqmap[SBSA_EHCI]; > + hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base; > + int irq = sbsa_ref_irqmap[SBSA_XHCI]; > > - sysbus_create_simple("platform-ehci-usb", base, > + sysbus_create_simple("sysbus-xhci", base, > qdev_get_gpio_in(sms->gic, irq)); > } > > @@ -785,7 +785,7 @@ static void sbsa_ref_init(MachineState *machine) > > create_ahci(sms); > > - create_ehci(sms); > + create_xhci(sms); > > create_pcie(sms); > > -- > 2.34.1 > >