From: Bernhard Kohl <bernhard.kohl@nsn.com> To: kvm@vger.kernel.org Subject: [PATCH] KVM: IOAPIC: Do not check polarity Date: Fri, 13 Mar 2009 10:53:02 +0000 (UTC) [thread overview] Message-ID: <loom.20090313T105104-837@post.gmane.org> (raw) NSN's proprietary OS DMX heavily depends on a correct BIOS MP table. >From there it also gets the information for initialization of PCI devices. We defined the polarity and trigger mode as for standard PCI devices "low level". The OS programs the ioapic the same way. Nothing else in QEMU's and KVM's IRQ, PIC, IOAPIC and LAPIC code cares about interrupt polarity. The "level" is always used as a logical value. So we must not change the level here. If we do so, PCI low level interrupts are not fired if the guest raises the interrupt (level=1), but first if it is reset again (level=0). This can result in infinite waiting for a single interupt. For example the DMX guest waits for the link up interupt of the E1000 ethernet device before enabling the TX and RX interupts of this device. E1000 emulation sets level=1, no interrupt is fired, deadlock. This does not happen if we use the -no-kvm-irqchip option. This means that qemu's ioapic does not care about the polarity and kvm's ioapic shouldn't do either. Signed-off-by: Bernhard Kohl <bernhard.kohl@nsn.com> --- virt/kvm/ioapic.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/virt/kvm/ioapic.c b/virt/kvm/ioapic.c index 1eddae9..4deb8e1 100644 --- a/virt/kvm/ioapic.c +++ b/virt/kvm/ioapic.c @@ -180,7 +180,6 @@ int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level) if (irq >= 0 && irq < IOAPIC_NUM_PINS) { entry = ioapic->redirtbl[irq]; - level ^= entry.fields.polarity; if (!level) ioapic->irr &= ~mask; else { -- 1.6.0.6
next reply other threads:[~2009-03-13 10:53 UTC|newest] Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top 2009-03-13 10:53 Bernhard Kohl [this message] 2009-03-15 10:38 ` Avi Kivity 2009-03-16 22:30 ` Bernhard Kohl
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