From mboxrd@z Thu Jan  1 00:00:00 1970
From: Tony Wang <wrd7612@163.com>
Date: Fri, 17 Sep 2010 08:01:21 +0000 (UTC)
Subject: [U-Boot] P4080 Reset Vector
References: <29641685.post@talk.nabble.com><loom.20100910T090157-423@post.gmane.org><2AE89BEB-B902-4BF9-8EC5-9AEAC8DD9870@kernel.crashing.org><loom.20100914T052720-40@post.gmane.org><50260780A060C94D9E98AC2670936D6020BB56@zch01exm21.fsl.freescale.net>
	<loom.20100915T100549-687@post.gmane.org>
	<50260780A060C94D9E98AC2670936D6020BD42@zch01exm21.fsl.freescale.net>
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Liu Dave-R63238 <r63238 <at> freescale.com> writes:

> 
> > For that reset address question, I think because p4080ds's FPGA can do
> this address
> > decode and map 0xefffxxxx to 0xffffxxxx setting by SW7, is it right?
> 
> No. FPGA doesn't matter with it.
> 
> The e500mc core boot start address(0xFFFF_FFFC) will point to the end of
> CS0 Flash due to OR0[AM]=0.
> In this phase, the core is using the relative addressing.
> After you change the BR0,OR0, you can use absolute addressing.
> 
> Keep in mind, the bootloader is placed to the end of CS0, and the RCW is
> placed to the start of CS0.
> 
> > I also has another quesition, if I choose boot from bank0, why RCW
> should be
> > programmed into address 0xe8000000? is it a rule of chip design?
> 

 Thanks Dave, 

It look same as other PQ2/3 which using BR0/OR0 to set boot vecror base address.

just confirm, do you know CPU will read RCW data before it jump to 0xFFFF_FFFC?

/Tony