From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932757Ab2JZMsV (ORCPT ); Fri, 26 Oct 2012 08:48:21 -0400 Received: from mga09.intel.com ([134.134.136.24]:65209 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932740Ab2JZMsS (ORCPT ); Fri, 26 Oct 2012 08:48:18 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.80,654,1344236400"; d="scan'208";a="232902316" From: Andi Kleen To: Michel Lespinasse Cc: Linus Torvalds , Rik van Riel , Peter Zijlstra , Andrea Arcangeli , Mel Gorman , Johannes Weiner , Thomas Gleixner , Andrew Morton , linux-kernel@vger.kernel.org, linux-mm@kvack.org, Ingo Molnar Subject: Re: [PATCH 05/31] x86/mm: Reduce tlb flushes from ptep_set_access_flags() References: <20121025121617.617683848@chello.nl> <20121025124832.840241082@chello.nl> <5089F5B5.1050206@redhat.com> <508A0A0D.4090001@redhat.com> Date: Fri, 26 Oct 2012 05:48:03 -0700 In-Reply-To: (Michel Lespinasse's message of "Fri, 26 Oct 2012 05:34:02 -0700") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Michel Lespinasse writes: > On Thu, Oct 25, 2012 at 9:23 PM, Linus Torvalds > wrote: >> On Thu, Oct 25, 2012 at 8:57 PM, Rik van Riel wrote: >>> >>> That may not even be needed. Apparently Intel chips >>> automatically flush an entry from the TLB when it >>> causes a page fault. I assume AMD chips do the same, >>> because flush_tlb_fix_spurious_fault evaluates to >>> nothing on x86. >> >> Yes. It's not architected as far as I know, though. But I agree, it's >> possible - even likely - we could avoid TLB flushing entirely on x86. > > Actually, it is architected on x86. This was first described in the > intel appnote 317080 "TLBs, Paging-Structure Caches, and Their > Invalidation", last paragraph of section 5.1. Nowadays, the same > contents are buried somewhere in Volume 3 of the architecture manual > (in my copy: 4.10.4.1 Operations that Invalidate TLBs and > Paging-Structure Caches) This unfortunately would only work for processes with no threads because it only works on the current logical CPU. -Andi -- ak@linux.intel.com -- Speaking for myself only From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from psmtp.com (na3sys010amx108.postini.com [74.125.245.108]) by kanga.kvack.org (Postfix) with SMTP id 920796B0072 for ; Fri, 26 Oct 2012 08:48:14 -0400 (EDT) From: Andi Kleen Subject: Re: [PATCH 05/31] x86/mm: Reduce tlb flushes from ptep_set_access_flags() References: <20121025121617.617683848@chello.nl> <20121025124832.840241082@chello.nl> <5089F5B5.1050206@redhat.com> <508A0A0D.4090001@redhat.com> Date: Fri, 26 Oct 2012 05:48:03 -0700 In-Reply-To: (Michel Lespinasse's message of "Fri, 26 Oct 2012 05:34:02 -0700") Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Sender: owner-linux-mm@kvack.org List-ID: To: Michel Lespinasse Cc: Linus Torvalds , Rik van Riel , Peter Zijlstra , Andrea Arcangeli , Mel Gorman , Johannes Weiner , Thomas Gleixner , Andrew Morton , linux-kernel@vger.kernel.org, linux-mm@kvack.org, Ingo Molnar Michel Lespinasse writes: > On Thu, Oct 25, 2012 at 9:23 PM, Linus Torvalds > wrote: >> On Thu, Oct 25, 2012 at 8:57 PM, Rik van Riel wrote: >>> >>> That may not even be needed. Apparently Intel chips >>> automatically flush an entry from the TLB when it >>> causes a page fault. I assume AMD chips do the same, >>> because flush_tlb_fix_spurious_fault evaluates to >>> nothing on x86. >> >> Yes. It's not architected as far as I know, though. But I agree, it's >> possible - even likely - we could avoid TLB flushing entirely on x86. > > Actually, it is architected on x86. This was first described in the > intel appnote 317080 "TLBs, Paging-Structure Caches, and Their > Invalidation", last paragraph of section 5.1. Nowadays, the same > contents are buried somewhere in Volume 3 of the architecture manual > (in my copy: 4.10.4.1 Operations that Invalidate TLBs and > Paging-Structure Caches) This unfortunately would only work for processes with no threads because it only works on the current logical CPU. -Andi -- ak@linux.intel.com -- Speaking for myself only -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org