From mboxrd@z Thu Jan 1 00:00:00 1970 From: Date: Tue, 19 Aug 2008 20:18:26 -0000 Subject: No subject Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de /* used to re-map FLASH both when starting from SRAM or FLASH: * restrict access enough to keep SRAM working (if any) * but not too much to meddle with FLASH accesses */ #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ I can see the above hash-defines being used in file=20 ./cpu/mpc8xx/cpu_init.c as follows (lines 176 to 178). /* now restrict to preliminary range */ memctl->memc_br0 =3D CFG_BR0_PRELIM; memctl->memc_or0 =3D CFG_OR0_PRELIM; where CFG_PRELIM_OR_AM is used in the definition of CFG_OR0_PRELIM, also in TQML860L.h (line 337). I read Table 15.4 of the Motorola MPC860 Family Users Manual=20 which explains the format of the OR registers. If I understand it=20 correctly, the definition of CFG_PRELIM_OR_AM limits the size of the Flash address range by masking out bits 0,1 and 2. Why are only three bits removed ?=20 Also, what puzzles me is the comment: restrict access enough to keep SRAM working (if any) but not too much to meddle with FLASH accesses Why do we have to restrict access to keep SRAM working ? Any explanations would be appreciated. Thanks, Charles. Dr Charles J Gillan The Institute of Electronics, Communications and Information Technology (ECIT), Queen's University Belfast, Titanic Quarter Queen=92s Road, Queen=92s Island,=20 Belfast, BT3 9DT Northern Ireland, UK =A0 Tel: +44 (0) 2890 971847