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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id q97sm3505687pjb.7.2020.04.16.12.12.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Apr 2020 12:12:11 -0700 (PDT) Date: Thu, 16 Apr 2020 12:12:11 -0700 (PDT) X-Google-Original-Date: Thu, 16 Apr 2020 12:12:08 PDT (-0700) Subject: Re: [PATCH v2 4/5] riscv: Use the XML target descriptions to report 3 system registers In-Reply-To: <1585668191-16287-5-git-send-email-vincent.chen@sifive.com> From: Palmer Dabbelt To: vincent.chen@sifive.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200416_121214_027589_16611B25 X-CRM114-Status: GOOD ( 20.49 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, kgdb-bugreport@lists.sourceforge.net, jason.wessel@windriver.com, dianders@chromium.org, vincent.chen@sifive.com, Paul Walmsley , linux-riscv@lists.infradead.org Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, 31 Mar 2020 08:23:10 PDT (-0700), vincent.chen@sifive.com wrote: > The $sstatus, $badaddr, and $scause registers belong to the thread context, > so KGDB can obtain their contents from pt_regs in each trap. However, the > sequential number of these registers in the gdb register list is far from > the general-purpose registers. If riscv port uses the existing method to > report these three registers, many trivial registers with sequence numbers > in the middle of them will also be packaged to the reply packets. To solve > this problem, the riscv port wants to introduce the GDB target description > mechanism to customize the reported register list. By the list, the KGDB > can ignore the intermediate registers and just reports the general-purpose > registers and these three system registers. > > Signed-off-by: Vincent Chen > --- > arch/riscv/Kconfig | 1 + > arch/riscv/include/asm/gdb_xml.h | 117 +++++++++++++++++++++++++++++++++++++++ > arch/riscv/include/asm/kgdb.h | 8 ++- > arch/riscv/kernel/kgdb.c | 14 +++++ > 4 files changed, 139 insertions(+), 1 deletion(-) > create mode 100644 arch/riscv/include/asm/gdb_xml.h > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 108794f4aa45..94b6f301007c 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -67,6 +67,7 @@ config RISCV > select HAVE_COPY_THREAD_TLS > select HAVE_ARCH_KASAN if MMU && 64BIT > select HAVE_ARCH_KGDB > + select ARCH_SUPPORTS_GDB_XML > > config ARCH_MMAP_RND_BITS_MIN > default 18 if 64BIT > diff --git a/arch/riscv/include/asm/gdb_xml.h b/arch/riscv/include/asm/gdb_xml.h > new file mode 100644 > index 000000000000..1d1459d06a1b > --- /dev/null > +++ b/arch/riscv/include/asm/gdb_xml.h > @@ -0,0 +1,117 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > + > +#ifndef __ASM_GDB_XML_H_ > +#define __ASM_GDB_XML_H_ > + > +#define arch_gdb_stub_feature riscv_gdb_stub_feature > +static const char riscv_gdb_stub_feature[64] = > + "PacketSize=800;qXfer:features:read+;"; > + > +static const char gdb_xfer_read_target[31] = "qXfer:features:read:target.xml:"; > + > +#ifdef CONFIG_64BIT > +static const char gdb_xfer_read_cpuxml[39] = > + "qXfer:features:read:riscv-64bit-cpu.xml"; > + > +static const char riscv_gdb_stub_target_desc[256] = > +"l" > +"" > +"" > +"" > +""; > + > +static const char riscv_gdb_stub_cpuxml[2048] = > +"l" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +""; > +#else > +static const char gdb_xfer_read_cpuxml[39] = > + "qXfer:features:read:riscv-32bit-cpu.xml"; > + > +static const char riscv_gdb_stub_target_desc[256] = > +"l" > +"" > +"" > +"" > +""; > + > +static const char riscv_gdb_stub_cpuxml[2048] = > +"l" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +"" > +""; > +#endif > +#endif > diff --git a/arch/riscv/include/asm/kgdb.h b/arch/riscv/include/asm/kgdb.h > index 69bc6a03081d..6c35a853940d 100644 > --- a/arch/riscv/include/asm/kgdb.h > +++ b/arch/riscv/include/asm/kgdb.h > @@ -7,7 +7,7 @@ > > #define GDB_SIZEOF_REG sizeof(unsigned long) > > -#define DBG_MAX_REG_NUM (33) > +#define DBG_MAX_REG_NUM (36) > #define NUMREGBYTES ((DBG_MAX_REG_NUM) * GDB_SIZEOF_REG) > #define CACHE_FLUSH_IS_SAFE 1 > #define BUFMAX 2048 > @@ -66,6 +66,9 @@ static inline void arch_kgdb_breakpoint(void) > #define DBG_REG_T5 "t5" > #define DBG_REG_T6 "t6" > #define DBG_REG_EPC "pc" > +#define DBG_REG_STATUS "sstatus" > +#define DBG_REG_BADADDR "stval" > +#define DBG_REG_CAUSE "scause" > > #define DBG_REG_ZERO_OFF 0 > #define DBG_REG_RA_OFF 1 > @@ -103,5 +106,8 @@ static inline void arch_kgdb_breakpoint(void) > #define DBG_REG_STATUS_OFF 33 > #define DBG_REG_BADADDR_OFF 34 > #define DBG_REG_CAUSE_OFF 35 > + > +#include > + > #endif > #endif > diff --git a/arch/riscv/kernel/kgdb.c b/arch/riscv/kernel/kgdb.c > index e3b1075c3935..86d891b7ea2c 100644 > --- a/arch/riscv/kernel/kgdb.c > +++ b/arch/riscv/kernel/kgdb.c > @@ -7,6 +7,7 @@ > #include > #include > #include > +#include > > enum { > NOT_KGDB_BREAK = 0, > @@ -48,6 +49,9 @@ struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = { > {DBG_REG_T5, GDB_SIZEOF_REG, offsetof(struct pt_regs, t5)}, > {DBG_REG_T6, GDB_SIZEOF_REG, offsetof(struct pt_regs, t6)}, > {DBG_REG_EPC, GDB_SIZEOF_REG, offsetof(struct pt_regs, epc)}, > + {DBG_REG_STATUS, GDB_SIZEOF_REG, offsetof(struct pt_regs, status)}, > + {DBG_REG_BADADDR, GDB_SIZEOF_REG, offsetof(struct pt_regs, badaddr)}, > + {DBG_REG_CAUSE, GDB_SIZEOF_REG, offsetof(struct pt_regs, cause)}, > }; > > char *dbg_get_reg(int regno, void *mem, struct pt_regs *regs) > @@ -100,6 +104,16 @@ void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long pc) > regs->epc = pc; > } > > +void arch_handle_qxfer_pkt(char *remcom_in_buffer, char *remcom_out_buffer) > +{ > + if (!strncmp(remcom_in_buffer, gdb_xfer_read_target, > + sizeof(gdb_xfer_read_target))) > + strcpy(remcom_out_buffer, riscv_gdb_stub_target_desc); > + else if (!strncmp(remcom_in_buffer, gdb_xfer_read_cpuxml, > + sizeof(gdb_xfer_read_cpuxml))) > + strcpy(remcom_out_buffer, riscv_gdb_stub_cpuxml); > +} > + > static inline void kgdb_arch_update_addr(struct pt_regs *regs, > char *remcom_in_buffer) > { Reviewed-by: Palmer Dabbelt