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From: Palmer Dabbelt <palmer@rivosinc.com>
To: mail@conchuod.ie
Cc: sboyd@kernel.org, mturquette@baylibre.com, aou@eecs.berkeley.edu,
	Paul Walmsley <paul.walmsley@sifive.com>,
	a.zummo@towertech.it, alexandre.belloni@bootlin.com,
	robh+dt@kernel.org,  krzk+dt@kernel.org,
	daire.mcnamara@microchip.com, linux-rtc@vger.kernel.org,
	devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-riscv@lists.infradead.org,  conor.dooley@microchip.com,
	atulkhare@rivosinc.com
Subject: Re: [PATCH v3 0/9] More PolarFire SoC Fixes for 5.18
Date: Fri, 22 Apr 2022 14:40:33 -0700 (PDT)	[thread overview]
Message-ID: <mhng-08dea5a1-77b8-4b79-93e3-cda9fffdf2ff@palmer-ri-x1c9> (raw)
In-Reply-To: <986c73df-9634-d18b-eed3-37584fa2ea89@conchuod.ie>

On Fri, 22 Apr 2022 14:10:55 PDT (-0700), mail@conchuod.ie wrote:
>
>
> On 22/04/2022 22:00, Stephen Boyd wrote:
>> Quoting Conor Dooley (2022-04-22 12:59:09)
>>> On 22/04/2022 20:39, Palmer Dabbelt wrote:
>>>>
>>>> Thanks.  These generally look good to me, but I don't see acks from everyone.  I'm perfectly fine treating these as fixes and taking them through the RISC-V tree, but looks like it's mostly clk stuff so
>>>>
>>>> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
>>>
>>> Ye, hopefully they go via clk. Stephen replied to v1 or 2 so
>>> I figure they're in his queue :)
>>
>> It helps to be explicit in the cover letter. It's in my queue but I put
>> it on hold because the cover letter didn't clarify what tree it was
>> intended for nor the priority of what is being fixed.
>
> Ah right, my bad. The coordinating things between trees stuff is
> still pretty new to me. If you could take the lot via clk, that'd
> be great?

No problem, the multi-tree stuff is always tricky.  It ended up in my 
queue too, but I fast-forward to the latest version of each set as I 
stumble into earlier ones so I guess I got here quickly.

Having these go through clk is better for me, I'll ignore them.

Thanks!

>> Is boot broken? Do I need to send these up to Linus next week as part of
>> fixes for this merge window?
>
> Boot is not broken, I was hoping this would go into 5.18 to avoid
> having to deal with two different sorts of reference clock DT
> entries - 5.18 where the DT provides the mss pll & 5.18+n where
> the DT provides the input to the mss pll.
>
> So, not next week urgent, but as fixes for this window please.
>
> Thanks,
> Conor.

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WARNING: multiple messages have this Message-ID
From: Palmer Dabbelt <palmer@rivosinc.com>
To: mail@conchuod.ie
Cc: sboyd@kernel.org, mturquette@baylibre.com, aou@eecs.berkeley.edu,
	Paul Walmsley <paul.walmsley@sifive.com>,
	a.zummo@towertech.it, alexandre.belloni@bootlin.com,
	robh+dt@kernel.org, krzk+dt@kernel.org,
	daire.mcnamara@microchip.com, linux-rtc@vger.kernel.org,
	devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-riscv@lists.infradead.org, conor.dooley@microchip.com,
	atulkhare@rivosinc.com
Subject: Re: [PATCH v3 0/9] More PolarFire SoC Fixes for 5.18
Date: Fri, 22 Apr 2022 14:40:33 -0700 (PDT)	[thread overview]
Message-ID: <mhng-08dea5a1-77b8-4b79-93e3-cda9fffdf2ff@palmer-ri-x1c9> (raw)
In-Reply-To: <986c73df-9634-d18b-eed3-37584fa2ea89@conchuod.ie>

On Fri, 22 Apr 2022 14:10:55 PDT (-0700), mail@conchuod.ie wrote:
>
>
> On 22/04/2022 22:00, Stephen Boyd wrote:
>> Quoting Conor Dooley (2022-04-22 12:59:09)
>>> On 22/04/2022 20:39, Palmer Dabbelt wrote:
>>>>
>>>> Thanks.  These generally look good to me, but I don't see acks from everyone.  I'm perfectly fine treating these as fixes and taking them through the RISC-V tree, but looks like it's mostly clk stuff so
>>>>
>>>> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
>>>
>>> Ye, hopefully they go via clk. Stephen replied to v1 or 2 so
>>> I figure they're in his queue :)
>>
>> It helps to be explicit in the cover letter. It's in my queue but I put
>> it on hold because the cover letter didn't clarify what tree it was
>> intended for nor the priority of what is being fixed.
>
> Ah right, my bad. The coordinating things between trees stuff is
> still pretty new to me. If you could take the lot via clk, that'd
> be great?

No problem, the multi-tree stuff is always tricky.  It ended up in my 
queue too, but I fast-forward to the latest version of each set as I 
stumble into earlier ones so I guess I got here quickly.

Having these go through clk is better for me, I'll ignore them.

Thanks!

>> Is boot broken? Do I need to send these up to Linus next week as part of
>> fixes for this merge window?
>
> Boot is not broken, I was hoping this would go into 5.18 to avoid
> having to deal with two different sorts of reference clock DT
> entries - 5.18 where the DT provides the mss pll & 5.18+n where
> the DT provides the input to the mss pll.
>
> So, not next week urgent, but as fixes for this window please.
>
> Thanks,
> Conor.

  reply	other threads:[~2022-04-22 21:40 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-13  7:58 [PATCH v3 0/9] More PolarFire SoC Fixes for 5.18 Conor Dooley
2022-04-13  7:58 ` Conor Dooley
2022-04-13  7:58 ` [PATCH v3 1/9] clk: microchip: mpfs: fix parents for FIC clocks Conor Dooley
2022-04-13  7:58   ` Conor Dooley
2022-04-23  1:41   ` Stephen Boyd
2022-04-23  1:41     ` Stephen Boyd
2022-04-23 17:58     ` Conor Dooley
2022-04-23 17:58       ` Conor Dooley
2022-04-13  7:58 ` [PATCH v3 2/9] clk: microchip: mpfs: mark CLK_ATHENA as critical Conor Dooley
2022-04-13  7:58   ` Conor Dooley
2022-04-23  1:41   ` Stephen Boyd
2022-04-23  1:41     ` Stephen Boyd
2022-04-13  7:58 ` [PATCH v3 3/9] riscv: dts: microchip: fix usage of fic clocks on mpfs Conor Dooley
2022-04-13  7:58   ` Conor Dooley
2022-04-23  1:41   ` Stephen Boyd
2022-04-23  1:41     ` Stephen Boyd
2022-04-13  7:58 ` [PATCH v3 4/9] dt-bindings: clk: mpfs document msspll dri registers Conor Dooley
2022-04-13  7:58   ` Conor Dooley
2022-04-23  1:41   ` Stephen Boyd
2022-04-23  1:41     ` Stephen Boyd
2022-04-13  7:58 ` [PATCH v3 5/9] dt-bindings: clk: mpfs: add defines for two new clocks Conor Dooley
2022-04-13  7:58   ` Conor Dooley
2022-04-19 11:59   ` Krzysztof Kozlowski
2022-04-19 11:59     ` Krzysztof Kozlowski
2022-04-23  1:41   ` Stephen Boyd
2022-04-23  1:41     ` Stephen Boyd
2022-04-13  7:58 ` [PATCH v3 6/9] dt-bindings: rtc: add refclk to mpfs-rtc Conor Dooley
2022-04-13  7:58   ` Conor Dooley
2022-04-23  1:41   ` Stephen Boyd
2022-04-23  1:41     ` Stephen Boyd
2022-04-13  7:58 ` [PATCH v3 7/9] clk: microchip: mpfs: re-parent the configurable clocks Conor Dooley
2022-04-13  7:58   ` Conor Dooley
2022-04-23  1:41   ` Stephen Boyd
2022-04-23  1:41     ` Stephen Boyd
2022-04-13  7:58 ` [PATCH v3 8/9] clk: microchip: mpfs: add RTCREF clock control Conor Dooley
2022-04-13  7:58   ` Conor Dooley
2022-04-23  1:42   ` Stephen Boyd
2022-04-23  1:42     ` Stephen Boyd
2022-04-13  7:58 ` [PATCH v3 9/9] riscv: dts: microchip: reparent mpfs clocks Conor Dooley
2022-04-13  7:58   ` Conor Dooley
2022-04-23  1:42   ` Stephen Boyd
2022-04-23  1:42     ` Stephen Boyd
2022-04-22 19:39 ` [PATCH v3 0/9] More PolarFire SoC Fixes for 5.18 Palmer Dabbelt
2022-04-22 19:39   ` Palmer Dabbelt
2022-04-22 19:59   ` Conor Dooley
2022-04-22 19:59     ` Conor Dooley
2022-04-22 21:00     ` Stephen Boyd
2022-04-22 21:00       ` Stephen Boyd
2022-04-22 21:10       ` Conor Dooley
2022-04-22 21:10         ` Conor Dooley
2022-04-22 21:40         ` Palmer Dabbelt [this message]
2022-04-22 21:40           ` Palmer Dabbelt
2022-04-22 21:52     ` Rob Herring
2022-04-22 21:52       ` Rob Herring
2022-04-22 22:32       ` Conor Dooley
2022-04-22 22:32         ` Conor Dooley

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