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Mon, 16 Sep 2019 11:28:59 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id a4sm12595350pfn.110.2019.09.16.11.28.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2019 11:28:58 -0700 (PDT) Date: Mon, 16 Sep 2019 11:28:58 -0700 (PDT) X-Google-Original-Date: Mon, 16 Sep 2019 11:28:52 PDT (-0700) Subject: Re: [PATCH RFC 11/14] arm64: Move the ASID allocator code in a separate file In-Reply-To: <20190916181800.7lfpt3t627byoomt@willie-the-truck> CC: Anup Patel , guoren@kernel.org, Will Deacon , julien.thierry@arm.com, aou@eecs.berkeley.edu, james.morse@arm.com, Arnd Bergmann , suzuki.poulose@arm.com, marc.zyngier@arm.com, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, rppt@linux.ibm.com, Christoph Hellwig , Atish Patra , julien.grall@arm.com, gary@garyguo.net, Paul Walmsley , christoffer.dall@arm.com, linux-riscv@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org From: Palmer Dabbelt To: will@kernel.org Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 16 Sep 2019 11:18:00 PDT (-0700), will@kernel.org wrote: > On Sun, Sep 15, 2019 at 05:03:38AM +0000, Anup Patel wrote: >> >> >> > -----Original Message----- >> > From: linux-kernel-owner@vger.kernel.org > > owner@vger.kernel.org> On Behalf Of Palmer Dabbelt >> > Sent: Saturday, September 14, 2019 7:31 PM >> > To: will@kernel.org >> > Cc: guoren@kernel.org; Will Deacon ; >> > julien.thierry@arm.com; aou@eecs.berkeley.edu; james.morse@arm.com; >> > Arnd Bergmann ; suzuki.poulose@arm.com; >> > marc.zyngier@arm.com; catalin.marinas@arm.com; Anup Patel >> > ; linux-kernel@vger.kernel.org; >> > rppt@linux.ibm.com; Christoph Hellwig ; Atish Patra >> > ; julien.grall@arm.com; gary@garyguo.net; Paul >> > Walmsley ; christoffer.dall@arm.com; linux- >> > riscv@lists.infradead.org; kvmarm@lists.cs.columbia.edu; linux-arm- >> > kernel@lists.infradead.org; iommu@lists.linux-foundation.org >> > Subject: Re: [PATCH RFC 11/14] arm64: Move the ASID allocator code in a >> > separate file >> > >> > On Thu, 12 Sep 2019 07:02:56 PDT (-0700), will@kernel.org wrote: >> > > On Sun, Sep 08, 2019 at 07:52:55AM +0800, Guo Ren wrote: >> > >> On Mon, Jun 24, 2019 at 6:40 PM Will Deacon wrote: >> > >> > > I'll keep my system use the same ASID for SMP + IOMMU :P >> > >> > >> > >> > You will want a separate allocator for that: >> > >> > >> > >> > https://lkml.kernel.org/r/20190610184714.6786-2-jean-philippe.bruck >> > >> > er@arm.com >> > >> >> > >> Yes, it is hard to maintain ASID between IOMMU and CPUMMU or >> > >> different system, because it's difficult to synchronize the IO_ASID >> > >> when the CPU ASID is rollover. >> > >> But we could still use hardware broadcast TLB invalidation >> > >> instruction to uniformly manage the ASID and IO_ASID, or OTHER_ASID in >> > our IOMMU. >> > > >> > > That's probably a bad idea, because you'll likely stall execution on >> > > the CPU until the IOTLB has completed invalidation. In the case of >> > > ATS, I think an endpoint ATC is permitted to take over a minute to >> > > respond. In reality, I suspect the worst you'll ever see would be in >> > > the msec range, but that's still an unacceptable period of time to hold a >> > CPU. >> > > >> > >> Welcome to join our disscusion: >> > >> "Introduce an implementation of IOMMU in linux-riscv" >> > >> 9 Sep 2019, 10:45 Jade-room-I&II (Corinthia Hotel Lisbon) RISC-V MC >> > > >> > > I attended this session, but it unfortunately raised many more >> > > questions than it answered. >> > >> > Ya, we're a long way from figuring this out. >> >> For everyone's reference, here is our first attempt at RISC-V ASID allocator: >> http://archive.lwn.net:8080/linux-kernel/20190329045111.14040-1-anup.patel@wdc.com/T/#u > > With a reply stating that the patch "absolutely does not work" ;) > > What exactly do you want people to do with that? It's an awful lot of effort > to review this sort of stuff and given that Guo Ren is talking about sharing > page tables between the CPU and an accelerator, maybe you're better off > stabilising Linux for the platforms that you can actually test rather than > getting so far ahead of yourselves that you end up with a bunch of wasted > work on patches that probably won't get merged any time soon. > > Seriously, they say "walk before you can run", but this is more "crawl > before you can fly". What's the rush? I agree, and I think I've been pretty clear here: we're not merging this ASID stuff until we have a platform we can test on, particularly as the platforms we have now already need some wacky hacks around TLB flushing that we haven't gotten to the bottom of. > Will From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0601C49ED7 for ; Mon, 16 Sep 2019 18:29:11 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BA3C1206C2 for ; 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Mon, 16 Sep 2019 11:28:59 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id a4sm12595350pfn.110.2019.09.16.11.28.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2019 11:28:58 -0700 (PDT) Date: Mon, 16 Sep 2019 11:28:58 -0700 (PDT) X-Google-Original-Date: Mon, 16 Sep 2019 11:28:52 PDT (-0700) Subject: Re: [PATCH RFC 11/14] arm64: Move the ASID allocator code in a separate file In-Reply-To: <20190916181800.7lfpt3t627byoomt@willie-the-truck> From: Palmer Dabbelt To: will@kernel.org Message-ID: Mime-Version: 1.0 (MHng) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190916_112902_858501_9C37AFAD X-CRM114-Status: GOOD ( 22.86 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: julien.thierry@arm.com, catalin.marinas@arm.com, Will Deacon , christoffer.dall@arm.com, Atish Patra , julien.grall@arm.com, guoren@kernel.org, gary@garyguo.net, linux-riscv@lists.infradead.org, kvmarm@lists.cs.columbia.edu, rppt@linux.ibm.com, Christoph Hellwig , aou@eecs.berkeley.edu, Arnd Bergmann , suzuki.poulose@arm.com, marc.zyngier@arm.com, Paul Walmsley , linux-arm-kernel@lists.infradead.org, Anup Patel , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, james.morse@arm.com Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, 16 Sep 2019 11:18:00 PDT (-0700), will@kernel.org wrote: > On Sun, Sep 15, 2019 at 05:03:38AM +0000, Anup Patel wrote: >> >> >> > -----Original Message----- >> > From: linux-kernel-owner@vger.kernel.org > > owner@vger.kernel.org> On Behalf Of Palmer Dabbelt >> > Sent: Saturday, September 14, 2019 7:31 PM >> > To: will@kernel.org >> > Cc: guoren@kernel.org; Will Deacon ; >> > julien.thierry@arm.com; aou@eecs.berkeley.edu; james.morse@arm.com; >> > Arnd Bergmann ; suzuki.poulose@arm.com; >> > marc.zyngier@arm.com; catalin.marinas@arm.com; Anup Patel >> > ; linux-kernel@vger.kernel.org; >> > rppt@linux.ibm.com; Christoph Hellwig ; Atish Patra >> > ; julien.grall@arm.com; gary@garyguo.net; Paul >> > Walmsley ; christoffer.dall@arm.com; linux- >> > riscv@lists.infradead.org; kvmarm@lists.cs.columbia.edu; linux-arm- >> > kernel@lists.infradead.org; iommu@lists.linux-foundation.org >> > Subject: Re: [PATCH RFC 11/14] arm64: Move the ASID allocator code in a >> > separate file >> > >> > On Thu, 12 Sep 2019 07:02:56 PDT (-0700), will@kernel.org wrote: >> > > On Sun, Sep 08, 2019 at 07:52:55AM +0800, Guo Ren wrote: >> > >> On Mon, Jun 24, 2019 at 6:40 PM Will Deacon wrote: >> > >> > > I'll keep my system use the same ASID for SMP + IOMMU :P >> > >> > >> > >> > You will want a separate allocator for that: >> > >> > >> > >> > https://lkml.kernel.org/r/20190610184714.6786-2-jean-philippe.bruck >> > >> > er@arm.com >> > >> >> > >> Yes, it is hard to maintain ASID between IOMMU and CPUMMU or >> > >> different system, because it's difficult to synchronize the IO_ASID >> > >> when the CPU ASID is rollover. >> > >> But we could still use hardware broadcast TLB invalidation >> > >> instruction to uniformly manage the ASID and IO_ASID, or OTHER_ASID in >> > our IOMMU. >> > > >> > > That's probably a bad idea, because you'll likely stall execution on >> > > the CPU until the IOTLB has completed invalidation. In the case of >> > > ATS, I think an endpoint ATC is permitted to take over a minute to >> > > respond. In reality, I suspect the worst you'll ever see would be in >> > > the msec range, but that's still an unacceptable period of time to hold a >> > CPU. >> > > >> > >> Welcome to join our disscusion: >> > >> "Introduce an implementation of IOMMU in linux-riscv" >> > >> 9 Sep 2019, 10:45 Jade-room-I&II (Corinthia Hotel Lisbon) RISC-V MC >> > > >> > > I attended this session, but it unfortunately raised many more >> > > questions than it answered. >> > >> > Ya, we're a long way from figuring this out. >> >> For everyone's reference, here is our first attempt at RISC-V ASID allocator: >> http://archive.lwn.net:8080/linux-kernel/20190329045111.14040-1-anup.patel@wdc.com/T/#u > > With a reply stating that the patch "absolutely does not work" ;) > > What exactly do you want people to do with that? It's an awful lot of effort > to review this sort of stuff and given that Guo Ren is talking about sharing > page tables between the CPU and an accelerator, maybe you're better off > stabilising Linux for the platforms that you can actually test rather than > getting so far ahead of yourselves that you end up with a bunch of wasted > work on patches that probably won't get merged any time soon. > > Seriously, they say "walk before you can run", but this is more "crawl > before you can fly". What's the rush? I agree, and I think I've been pretty clear here: we're not merging this ASID stuff until we have a platform we can test on, particularly as the platforms we have now already need some wacky hacks around TLB flushing that we haven't gotten to the bottom of. > Will _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26A51C49ED7 for ; Mon, 16 Sep 2019 18:29:40 +0000 (UTC) Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E3A0E206C2 for ; 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Mon, 16 Sep 2019 11:28:59 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id a4sm12595350pfn.110.2019.09.16.11.28.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2019 11:28:58 -0700 (PDT) Date: Mon, 16 Sep 2019 11:28:58 -0700 (PDT) X-Google-Original-Date: Mon, 16 Sep 2019 11:28:52 PDT (-0700) Subject: Re: [PATCH RFC 11/14] arm64: Move the ASID allocator code in a separate file In-Reply-To: <20190916181800.7lfpt3t627byoomt@willie-the-truck> From: Palmer Dabbelt To: will@kernel.org Message-ID: Mime-Version: 1.0 (MHng) Cc: julien.thierry@arm.com, catalin.marinas@arm.com, Will Deacon , christoffer.dall@arm.com, Atish Patra , julien.grall@arm.com, gary@garyguo.net, linux-riscv@lists.infradead.org, kvmarm@lists.cs.columbia.edu, rppt@linux.ibm.com, aou@eecs.berkeley.edu, Arnd Bergmann , suzuki.poulose@arm.com, marc.zyngier@arm.com, Paul Walmsley , linux-arm-kernel@lists.infradead.org, Anup Patel , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, james.morse@arm.com X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: iommu-bounces@lists.linux-foundation.org Errors-To: iommu-bounces@lists.linux-foundation.org On Mon, 16 Sep 2019 11:18:00 PDT (-0700), will@kernel.org wrote: > On Sun, Sep 15, 2019 at 05:03:38AM +0000, Anup Patel wrote: >> >> >> > -----Original Message----- >> > From: linux-kernel-owner@vger.kernel.org > > owner@vger.kernel.org> On Behalf Of Palmer Dabbelt >> > Sent: Saturday, September 14, 2019 7:31 PM >> > To: will@kernel.org >> > Cc: guoren@kernel.org; Will Deacon ; >> > julien.thierry@arm.com; aou@eecs.berkeley.edu; james.morse@arm.com; >> > Arnd Bergmann ; suzuki.poulose@arm.com; >> > marc.zyngier@arm.com; catalin.marinas@arm.com; Anup Patel >> > ; linux-kernel@vger.kernel.org; >> > rppt@linux.ibm.com; Christoph Hellwig ; Atish Patra >> > ; julien.grall@arm.com; gary@garyguo.net; Paul >> > Walmsley ; christoffer.dall@arm.com; linux- >> > riscv@lists.infradead.org; kvmarm@lists.cs.columbia.edu; linux-arm- >> > kernel@lists.infradead.org; iommu@lists.linux-foundation.org >> > Subject: Re: [PATCH RFC 11/14] arm64: Move the ASID allocator code in a >> > separate file >> > >> > On Thu, 12 Sep 2019 07:02:56 PDT (-0700), will@kernel.org wrote: >> > > On Sun, Sep 08, 2019 at 07:52:55AM +0800, Guo Ren wrote: >> > >> On Mon, Jun 24, 2019 at 6:40 PM Will Deacon wrote: >> > >> > > I'll keep my system use the same ASID for SMP + IOMMU :P >> > >> > >> > >> > You will want a separate allocator for that: >> > >> > >> > >> > https://lkml.kernel.org/r/20190610184714.6786-2-jean-philippe.bruck >> > >> > er@arm.com >> > >> >> > >> Yes, it is hard to maintain ASID between IOMMU and CPUMMU or >> > >> different system, because it's difficult to synchronize the IO_ASID >> > >> when the CPU ASID is rollover. >> > >> But we could still use hardware broadcast TLB invalidation >> > >> instruction to uniformly manage the ASID and IO_ASID, or OTHER_ASID in >> > our IOMMU. >> > > >> > > That's probably a bad idea, because you'll likely stall execution on >> > > the CPU until the IOTLB has completed invalidation. In the case of >> > > ATS, I think an endpoint ATC is permitted to take over a minute to >> > > respond. In reality, I suspect the worst you'll ever see would be in >> > > the msec range, but that's still an unacceptable period of time to hold a >> > CPU. >> > > >> > >> Welcome to join our disscusion: >> > >> "Introduce an implementation of IOMMU in linux-riscv" >> > >> 9 Sep 2019, 10:45 Jade-room-I&II (Corinthia Hotel Lisbon) RISC-V MC >> > > >> > > I attended this session, but it unfortunately raised many more >> > > questions than it answered. >> > >> > Ya, we're a long way from figuring this out. >> >> For everyone's reference, here is our first attempt at RISC-V ASID allocator: >> http://archive.lwn.net:8080/linux-kernel/20190329045111.14040-1-anup.patel@wdc.com/T/#u > > With a reply stating that the patch "absolutely does not work" ;) > > What exactly do you want people to do with that? It's an awful lot of effort > to review this sort of stuff and given that Guo Ren is talking about sharing > page tables between the CPU and an accelerator, maybe you're better off > stabilising Linux for the platforms that you can actually test rather than > getting so far ahead of yourselves that you end up with a bunch of wasted > work on patches that probably won't get merged any time soon. > > Seriously, they say "walk before you can run", but this is more "crawl > before you can fly". What's the rush? I agree, and I think I've been pretty clear here: we're not merging this ASID stuff until we have a platform we can test on, particularly as the platforms we have now already need some wacky hacks around TLB flushing that we haven't gotten to the bottom of. > Will _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39947C49ED7 for ; Mon, 16 Sep 2019 18:29:09 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id C0790206C2 for ; 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Mon, 16 Sep 2019 11:28:58 -0700 (PDT) Date: Mon, 16 Sep 2019 11:28:58 -0700 (PDT) X-Google-Original-Date: Mon, 16 Sep 2019 11:28:52 PDT (-0700) Subject: Re: [PATCH RFC 11/14] arm64: Move the ASID allocator code in a separate file In-Reply-To: <20190916181800.7lfpt3t627byoomt@willie-the-truck> From: Palmer Dabbelt To: will@kernel.org Message-ID: Mime-Version: 1.0 (MHng) Cc: catalin.marinas@arm.com, Will Deacon , Atish Patra , julien.grall@arm.com, guoren@kernel.org, gary@garyguo.net, linux-riscv@lists.infradead.org, kvmarm@lists.cs.columbia.edu, rppt@linux.ibm.com, Christoph Hellwig , aou@eecs.berkeley.edu, Arnd Bergmann , marc.zyngier@arm.com, Paul Walmsley , linux-arm-kernel@lists.infradead.org, Anup Patel , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Mon, 16 Sep 2019 11:18:00 PDT (-0700), will@kernel.org wrote: > On Sun, Sep 15, 2019 at 05:03:38AM +0000, Anup Patel wrote: >> >> >> > -----Original Message----- >> > From: linux-kernel-owner@vger.kernel.org > > owner@vger.kernel.org> On Behalf Of Palmer Dabbelt >> > Sent: Saturday, September 14, 2019 7:31 PM >> > To: will@kernel.org >> > Cc: guoren@kernel.org; Will Deacon ; >> > julien.thierry@arm.com; aou@eecs.berkeley.edu; james.morse@arm.com; >> > Arnd Bergmann ; suzuki.poulose@arm.com; >> > marc.zyngier@arm.com; catalin.marinas@arm.com; Anup Patel >> > ; linux-kernel@vger.kernel.org; >> > rppt@linux.ibm.com; Christoph Hellwig ; Atish Patra >> > ; julien.grall@arm.com; gary@garyguo.net; Paul >> > Walmsley ; christoffer.dall@arm.com; linux- >> > riscv@lists.infradead.org; kvmarm@lists.cs.columbia.edu; linux-arm- >> > kernel@lists.infradead.org; iommu@lists.linux-foundation.org >> > Subject: Re: [PATCH RFC 11/14] arm64: Move the ASID allocator code in a >> > separate file >> > >> > On Thu, 12 Sep 2019 07:02:56 PDT (-0700), will@kernel.org wrote: >> > > On Sun, Sep 08, 2019 at 07:52:55AM +0800, Guo Ren wrote: >> > >> On Mon, Jun 24, 2019 at 6:40 PM Will Deacon wrote: >> > >> > > I'll keep my system use the same ASID for SMP + IOMMU :P >> > >> > >> > >> > You will want a separate allocator for that: >> > >> > >> > >> > https://lkml.kernel.org/r/20190610184714.6786-2-jean-philippe.bruck >> > >> > er@arm.com >> > >> >> > >> Yes, it is hard to maintain ASID between IOMMU and CPUMMU or >> > >> different system, because it's difficult to synchronize the IO_ASID >> > >> when the CPU ASID is rollover. >> > >> But we could still use hardware broadcast TLB invalidation >> > >> instruction to uniformly manage the ASID and IO_ASID, or OTHER_ASID in >> > our IOMMU. >> > > >> > > That's probably a bad idea, because you'll likely stall execution on >> > > the CPU until the IOTLB has completed invalidation. In the case of >> > > ATS, I think an endpoint ATC is permitted to take over a minute to >> > > respond. In reality, I suspect the worst you'll ever see would be in >> > > the msec range, but that's still an unacceptable period of time to hold a >> > CPU. >> > > >> > >> Welcome to join our disscusion: >> > >> "Introduce an implementation of IOMMU in linux-riscv" >> > >> 9 Sep 2019, 10:45 Jade-room-I&II (Corinthia Hotel Lisbon) RISC-V MC >> > > >> > > I attended this session, but it unfortunately raised many more >> > > questions than it answered. >> > >> > Ya, we're a long way from figuring this out. >> >> For everyone's reference, here is our first attempt at RISC-V ASID allocator: >> http://archive.lwn.net:8080/linux-kernel/20190329045111.14040-1-anup.patel@wdc.com/T/#u > > With a reply stating that the patch "absolutely does not work" ;) > > What exactly do you want people to do with that? It's an awful lot of effort > to review this sort of stuff and given that Guo Ren is talking about sharing > page tables between the CPU and an accelerator, maybe you're better off > stabilising Linux for the platforms that you can actually test rather than > getting so far ahead of yourselves that you end up with a bunch of wasted > work on patches that probably won't get merged any time soon. > > Seriously, they say "walk before you can run", but this is more "crawl > before you can fly". What's the rush? I agree, and I think I've been pretty clear here: we're not merging this ASID stuff until we have a platform we can test on, particularly as the platforms we have now already need some wacky hacks around TLB flushing that we haven't gotten to the bottom of. > Will _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75624C49ED7 for ; Mon, 16 Sep 2019 18:29:24 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 49B6C206C2 for ; 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Mon, 16 Sep 2019 11:28:59 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id a4sm12595350pfn.110.2019.09.16.11.28.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2019 11:28:58 -0700 (PDT) Date: Mon, 16 Sep 2019 11:28:58 -0700 (PDT) X-Google-Original-Date: Mon, 16 Sep 2019 11:28:52 PDT (-0700) Subject: Re: [PATCH RFC 11/14] arm64: Move the ASID allocator code in a separate file In-Reply-To: <20190916181800.7lfpt3t627byoomt@willie-the-truck> From: Palmer Dabbelt To: will@kernel.org Message-ID: Mime-Version: 1.0 (MHng) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190916_112902_888841_8B47E90B X-CRM114-Status: GOOD ( 24.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: julien.thierry@arm.com, catalin.marinas@arm.com, Will Deacon , christoffer.dall@arm.com, Atish Patra , julien.grall@arm.com, guoren@kernel.org, gary@garyguo.net, linux-riscv@lists.infradead.org, kvmarm@lists.cs.columbia.edu, rppt@linux.ibm.com, Christoph Hellwig , aou@eecs.berkeley.edu, Arnd Bergmann , suzuki.poulose@arm.com, marc.zyngier@arm.com, Paul Walmsley , linux-arm-kernel@lists.infradead.org, Anup Patel , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, james.morse@arm.com Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 16 Sep 2019 11:18:00 PDT (-0700), will@kernel.org wrote: > On Sun, Sep 15, 2019 at 05:03:38AM +0000, Anup Patel wrote: >> >> >> > -----Original Message----- >> > From: linux-kernel-owner@vger.kernel.org > > owner@vger.kernel.org> On Behalf Of Palmer Dabbelt >> > Sent: Saturday, September 14, 2019 7:31 PM >> > To: will@kernel.org >> > Cc: guoren@kernel.org; Will Deacon ; >> > julien.thierry@arm.com; aou@eecs.berkeley.edu; james.morse@arm.com; >> > Arnd Bergmann ; suzuki.poulose@arm.com; >> > marc.zyngier@arm.com; catalin.marinas@arm.com; Anup Patel >> > ; linux-kernel@vger.kernel.org; >> > rppt@linux.ibm.com; Christoph Hellwig ; Atish Patra >> > ; julien.grall@arm.com; gary@garyguo.net; Paul >> > Walmsley ; christoffer.dall@arm.com; linux- >> > riscv@lists.infradead.org; kvmarm@lists.cs.columbia.edu; linux-arm- >> > kernel@lists.infradead.org; iommu@lists.linux-foundation.org >> > Subject: Re: [PATCH RFC 11/14] arm64: Move the ASID allocator code in a >> > separate file >> > >> > On Thu, 12 Sep 2019 07:02:56 PDT (-0700), will@kernel.org wrote: >> > > On Sun, Sep 08, 2019 at 07:52:55AM +0800, Guo Ren wrote: >> > >> On Mon, Jun 24, 2019 at 6:40 PM Will Deacon wrote: >> > >> > > I'll keep my system use the same ASID for SMP + IOMMU :P >> > >> > >> > >> > You will want a separate allocator for that: >> > >> > >> > >> > https://lkml.kernel.org/r/20190610184714.6786-2-jean-philippe.bruck >> > >> > er@arm.com >> > >> >> > >> Yes, it is hard to maintain ASID between IOMMU and CPUMMU or >> > >> different system, because it's difficult to synchronize the IO_ASID >> > >> when the CPU ASID is rollover. >> > >> But we could still use hardware broadcast TLB invalidation >> > >> instruction to uniformly manage the ASID and IO_ASID, or OTHER_ASID in >> > our IOMMU. >> > > >> > > That's probably a bad idea, because you'll likely stall execution on >> > > the CPU until the IOTLB has completed invalidation. In the case of >> > > ATS, I think an endpoint ATC is permitted to take over a minute to >> > > respond. In reality, I suspect the worst you'll ever see would be in >> > > the msec range, but that's still an unacceptable period of time to hold a >> > CPU. >> > > >> > >> Welcome to join our disscusion: >> > >> "Introduce an implementation of IOMMU in linux-riscv" >> > >> 9 Sep 2019, 10:45 Jade-room-I&II (Corinthia Hotel Lisbon) RISC-V MC >> > > >> > > I attended this session, but it unfortunately raised many more >> > > questions than it answered. >> > >> > Ya, we're a long way from figuring this out. >> >> For everyone's reference, here is our first attempt at RISC-V ASID allocator: >> http://archive.lwn.net:8080/linux-kernel/20190329045111.14040-1-anup.patel@wdc.com/T/#u > > With a reply stating that the patch "absolutely does not work" ;) > > What exactly do you want people to do with that? It's an awful lot of effort > to review this sort of stuff and given that Guo Ren is talking about sharing > page tables between the CPU and an accelerator, maybe you're better off > stabilising Linux for the platforms that you can actually test rather than > getting so far ahead of yourselves that you end up with a bunch of wasted > work on patches that probably won't get merged any time soon. > > Seriously, they say "walk before you can run", but this is more "crawl > before you can fly". What's the rush? I agree, and I think I've been pretty clear here: we're not merging this ASID stuff until we have a platform we can test on, particularly as the platforms we have now already need some wacky hacks around TLB flushing that we haven't gotten to the bottom of. > Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel