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Mon, 20 Mar 2023 16:46:28 -0700 (PDT) Date: Mon, 20 Mar 2023 16:46:28 -0700 (PDT) X-Google-Original-Date: Mon, 20 Mar 2023 16:45:32 PDT (-0700) Subject: Re: [PATCH 01/12] dt-bindings: riscv: sifive-ccache: Add compatible for StarFive JH7100 SoC In-Reply-To: CC: cristian.ciocaltea@collabora.com, lee@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, kernel@esmil.dk, Paul Walmsley , aou@eecs.berkeley.edu, peppe.cavallaro@st.com, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, richardcochran@gmail.com, sagar.kadam@sifive.com, yanhong.wang@starfivetech.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com From: Palmer Dabbelt To: Conor Dooley Message-ID: Mime-Version: 1.0 (MHng) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230320_164631_961204_E73AC14F X-CRM114-Status: GOOD ( 25.58 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, 14 Feb 2023 12:40:35 PST (-0800), Conor Dooley wrote: > Hey all, > > On Sat, Feb 11, 2023 at 05:18:10AM +0200, Cristian Ciocaltea wrote: >> Document the compatible for the SiFive Composable Cache Controller found >> on the StarFive JH7100 SoC. >> >> This also requires extending the 'reg' property to handle distinct >> ranges, as specified via 'reg-names'. >> >> Signed-off-by: Cristian Ciocaltea >> --- >> .../bindings/riscv/sifive,ccache0.yaml | 28 ++++++++++++++++++- >> 1 file changed, 27 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml >> index 31d20efaa6d3..2b864b2f12c9 100644 >> --- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml >> +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml >> @@ -25,6 +25,7 @@ select: >> - sifive,ccache0 >> - sifive,fu540-c000-ccache >> - sifive,fu740-c000-ccache >> + - starfive,jh7100-ccache >> >> required: >> - compatible >> @@ -37,6 +38,7 @@ properties: >> - sifive,ccache0 >> - sifive,fu540-c000-ccache >> - sifive,fu740-c000-ccache >> + - starfive,jh7100-ccache >> - const: cache >> - items: >> - const: starfive,jh7110-ccache >> @@ -70,7 +72,13 @@ properties: >> - description: DirFail interrupt >> >> reg: >> - maxItems: 1 >> + minItems: 1 >> + maxItems: 2 >> + >> + reg-names: >> + items: >> + - const: control >> + - const: sideband > > So why is this called "sideband"? > In the docs for the JH7100 it is called LIM & it's called LIM in our > docs for the PolarFire SoC (at the same address btw) and we run the HSS IIRC it's both: "LIM" is the memory, "sideband" is the port. I can't find any proper documentation of "sideband" outside of DT and errata, but there's a hanful of references to it in the bootloader for the fu540: . It's not really clear which is more correct here: sideband accesses are only useful when the cache is configured as an LIM, at least for general software. IIRC the accesses to the LIM only go through the sideband port for the E core, but I might be wrong about that. > out of it! LIM being "loosely integrated memory", which by the limit > hits on Google may be a SiFive-ism? Yep: TIM is the SiFive version of Arm's TCM (tightly coupled memory), and LIM is the flavor that's farther away (L2 instead of L1). > I'm not really sure if adding it as a "reg" section is the right thing > to do as it's not "just" a register bank. > Perhaps Rob/Krzysztof have a take on that one? > >> >> next-level-cache: true >> >> @@ -89,6 +97,7 @@ allOf: >> contains: >> enum: >> - sifive,fu740-c000-ccache >> + - starfive,jh7100-ccache >> - starfive,jh7110-ccache >> - microchip,mpfs-ccache >> >> @@ -106,12 +115,29 @@ allOf: >> Must contain entries for DirError, DataError and DataFail signals. >> maxItems: 3 >> >> + - if: >> + properties: >> + compatible: >> + contains: >> + const: starfive,jh7100-ccache >> + >> + then: >> + properties: >> + reg: >> + maxItems: 2 >> + >> + else: >> + properties: >> + reg: >> + maxItems: 1 >> + >> - if: >> properties: >> compatible: >> contains: >> enum: >> - sifive,fu740-c000-ccache >> + - starfive,jh7100-ccache >> - starfive,jh7110-ccache >> >> then: >> -- >> 2.39.1 >> _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B960EC6FD1D for ; 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Mon, 20 Mar 2023 16:46:28 -0700 (PDT) Date: Mon, 20 Mar 2023 16:46:28 -0700 (PDT) X-Google-Original-Date: Mon, 20 Mar 2023 16:45:32 PDT (-0700) Subject: Re: [PATCH 01/12] dt-bindings: riscv: sifive-ccache: Add compatible for StarFive JH7100 SoC In-Reply-To: CC: cristian.ciocaltea@collabora.com, lee@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, kernel@esmil.dk, Paul Walmsley , aou@eecs.berkeley.edu, peppe.cavallaro@st.com, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, richardcochran@gmail.com, sagar.kadam@sifive.com, yanhong.wang@starfivetech.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com From: Palmer Dabbelt To: Conor Dooley Message-ID: Mime-Version: 1.0 (MHng) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230320_164631_959365_51092A84 X-CRM114-Status: GOOD ( 27.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 14 Feb 2023 12:40:35 PST (-0800), Conor Dooley wrote: > Hey all, > > On Sat, Feb 11, 2023 at 05:18:10AM +0200, Cristian Ciocaltea wrote: >> Document the compatible for the SiFive Composable Cache Controller found >> on the StarFive JH7100 SoC. >> >> This also requires extending the 'reg' property to handle distinct >> ranges, as specified via 'reg-names'. >> >> Signed-off-by: Cristian Ciocaltea >> --- >> .../bindings/riscv/sifive,ccache0.yaml | 28 ++++++++++++++++++- >> 1 file changed, 27 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml >> index 31d20efaa6d3..2b864b2f12c9 100644 >> --- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml >> +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml >> @@ -25,6 +25,7 @@ select: >> - sifive,ccache0 >> - sifive,fu540-c000-ccache >> - sifive,fu740-c000-ccache >> + - starfive,jh7100-ccache >> >> required: >> - compatible >> @@ -37,6 +38,7 @@ properties: >> - sifive,ccache0 >> - sifive,fu540-c000-ccache >> - sifive,fu740-c000-ccache >> + - starfive,jh7100-ccache >> - const: cache >> - items: >> - const: starfive,jh7110-ccache >> @@ -70,7 +72,13 @@ properties: >> - description: DirFail interrupt >> >> reg: >> - maxItems: 1 >> + minItems: 1 >> + maxItems: 2 >> + >> + reg-names: >> + items: >> + - const: control >> + - const: sideband > > So why is this called "sideband"? > In the docs for the JH7100 it is called LIM & it's called LIM in our > docs for the PolarFire SoC (at the same address btw) and we run the HSS IIRC it's both: "LIM" is the memory, "sideband" is the port. I can't find any proper documentation of "sideband" outside of DT and errata, but there's a hanful of references to it in the bootloader for the fu540: . It's not really clear which is more correct here: sideband accesses are only useful when the cache is configured as an LIM, at least for general software. IIRC the accesses to the LIM only go through the sideband port for the E core, but I might be wrong about that. > out of it! LIM being "loosely integrated memory", which by the limit > hits on Google may be a SiFive-ism? Yep: TIM is the SiFive version of Arm's TCM (tightly coupled memory), and LIM is the flavor that's farther away (L2 instead of L1). > I'm not really sure if adding it as a "reg" section is the right thing > to do as it's not "just" a register bank. > Perhaps Rob/Krzysztof have a take on that one? > >> >> next-level-cache: true >> >> @@ -89,6 +97,7 @@ allOf: >> contains: >> enum: >> - sifive,fu740-c000-ccache >> + - starfive,jh7100-ccache >> - starfive,jh7110-ccache >> - microchip,mpfs-ccache >> >> @@ -106,12 +115,29 @@ allOf: >> Must contain entries for DirError, DataError and DataFail signals. >> maxItems: 3 >> >> + - if: >> + properties: >> + compatible: >> + contains: >> + const: starfive,jh7100-ccache >> + >> + then: >> + properties: >> + reg: >> + maxItems: 2 >> + >> + else: >> + properties: >> + reg: >> + maxItems: 1 >> + >> - if: >> properties: >> compatible: >> contains: >> enum: >> - sifive,fu740-c000-ccache >> + - starfive,jh7100-ccache >> - starfive,jh7110-ccache >> >> then: >> -- >> 2.39.1 >> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 329FFC7618D for ; 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Mon, 20 Mar 2023 16:46:29 -0700 (PDT) Received: from localhost ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id 30-20020a630c5e000000b00502fd141ffbsm6756689pgm.49.2023.03.20.16.46.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Mar 2023 16:46:28 -0700 (PDT) Date: Mon, 20 Mar 2023 16:46:28 -0700 (PDT) X-Google-Original-Date: Mon, 20 Mar 2023 16:45:32 PDT (-0700) Subject: Re: [PATCH 01/12] dt-bindings: riscv: sifive-ccache: Add compatible for StarFive JH7100 SoC In-Reply-To: CC: cristian.ciocaltea@collabora.com, lee@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, kernel@esmil.dk, Paul Walmsley , aou@eecs.berkeley.edu, peppe.cavallaro@st.com, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, richardcochran@gmail.com, sagar.kadam@sifive.com, yanhong.wang@starfivetech.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com From: Palmer Dabbelt To: Conor Dooley Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 14 Feb 2023 12:40:35 PST (-0800), Conor Dooley wrote: > Hey all, > > On Sat, Feb 11, 2023 at 05:18:10AM +0200, Cristian Ciocaltea wrote: >> Document the compatible for the SiFive Composable Cache Controller found >> on the StarFive JH7100 SoC. >> >> This also requires extending the 'reg' property to handle distinct >> ranges, as specified via 'reg-names'. >> >> Signed-off-by: Cristian Ciocaltea >> --- >> .../bindings/riscv/sifive,ccache0.yaml | 28 ++++++++++++++++++- >> 1 file changed, 27 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml >> index 31d20efaa6d3..2b864b2f12c9 100644 >> --- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml >> +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml >> @@ -25,6 +25,7 @@ select: >> - sifive,ccache0 >> - sifive,fu540-c000-ccache >> - sifive,fu740-c000-ccache >> + - starfive,jh7100-ccache >> >> required: >> - compatible >> @@ -37,6 +38,7 @@ properties: >> - sifive,ccache0 >> - sifive,fu540-c000-ccache >> - sifive,fu740-c000-ccache >> + - starfive,jh7100-ccache >> - const: cache >> - items: >> - const: starfive,jh7110-ccache >> @@ -70,7 +72,13 @@ properties: >> - description: DirFail interrupt >> >> reg: >> - maxItems: 1 >> + minItems: 1 >> + maxItems: 2 >> + >> + reg-names: >> + items: >> + - const: control >> + - const: sideband > > So why is this called "sideband"? > In the docs for the JH7100 it is called LIM & it's called LIM in our > docs for the PolarFire SoC (at the same address btw) and we run the HSS IIRC it's both: "LIM" is the memory, "sideband" is the port. I can't find any proper documentation of "sideband" outside of DT and errata, but there's a hanful of references to it in the bootloader for the fu540: . It's not really clear which is more correct here: sideband accesses are only useful when the cache is configured as an LIM, at least for general software. IIRC the accesses to the LIM only go through the sideband port for the E core, but I might be wrong about that. > out of it! LIM being "loosely integrated memory", which by the limit > hits on Google may be a SiFive-ism? Yep: TIM is the SiFive version of Arm's TCM (tightly coupled memory), and LIM is the flavor that's farther away (L2 instead of L1). > I'm not really sure if adding it as a "reg" section is the right thing > to do as it's not "just" a register bank. > Perhaps Rob/Krzysztof have a take on that one? > >> >> next-level-cache: true >> >> @@ -89,6 +97,7 @@ allOf: >> contains: >> enum: >> - sifive,fu740-c000-ccache >> + - starfive,jh7100-ccache >> - starfive,jh7110-ccache >> - microchip,mpfs-ccache >> >> @@ -106,12 +115,29 @@ allOf: >> Must contain entries for DirError, DataError and DataFail signals. >> maxItems: 3 >> >> + - if: >> + properties: >> + compatible: >> + contains: >> + const: starfive,jh7100-ccache >> + >> + then: >> + properties: >> + reg: >> + maxItems: 2 >> + >> + else: >> + properties: >> + reg: >> + maxItems: 1 >> + >> - if: >> properties: >> compatible: >> contains: >> enum: >> - sifive,fu740-c000-ccache >> + - starfive,jh7100-ccache >> - starfive,jh7110-ccache >> >> then: >> -- >> 2.39.1 >>