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In-Reply-To: CC: rajnesh.kanwal49@gmail.com, josemartins90@gmail.com, qemu-riscv@nongnu.org, Alistair Francis , qemu-devel@nongnu.org From: Palmer Dabbelt To: alistair23@gmail.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, 26 Feb 2020 09:55:34 PST (-0800), alistair23@gmail.com wrote: > On Wed, Feb 26, 2020 at 12:54 AM Rajnesh Kanwal > wrote: >> >> Here is the link to the patch >> https://lists.nongnu.org/archive/html/qemu-riscv/2020-01/msg00191.html > > Ah, it doesn't look like it made it to the QEMU-devel list. Can you > re-send it to QEMU-devel? I can't find the older patch in my inbox, so I'm just taking this one. > > Alistair > >> >> -Rajnesh >> >> On Tue, Feb 25, 2020 at 12:06 AM Alistair Francis wrote: >>> >>> On Sun, Feb 23, 2020 at 11:23 AM Jose Martins wrote: >>> > >>> > Hello rajnesh, >>> > >>> > I had already submitted almost this exact patch a few weeks ago. >>> >>> To QEMU? I don't see the patch. >>> >>> Alistair >>> >>> > >>> > Jose >>> > >>> > On Sun, 23 Feb 2020 at 13:51, wrote: >>> > > >>> > > From: Rajnesh Kanwal >>> > > >>> > > Currently riscv_cpu_local_irq_pending is used to find out pending >>> > > interrupt and VS mode interrupts are being shifted to represent >>> > > S mode interrupts in this function. So when the cause returned by >>> > > this function is passed to riscv_cpu_do_interrupt to actually >>> > > forward the interrupt, the VS mode forwarding check does not work >>> > > as intended and interrupt is actually forwarded to hypervisor. This >>> > > patch fixes this issue. >>> > > >>> > > Signed-off-by: Rajnesh Kanwal >>> > > --- >>> > > target/riscv/cpu_helper.c | 9 ++++++++- >>> > > 1 file changed, 8 insertions(+), 1 deletion(-) >>> > > >>> > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c >>> > > index b9e90dfd9a..59535ecba6 100644 >>> > > --- a/target/riscv/cpu_helper.c >>> > > +++ b/target/riscv/cpu_helper.c >>> > > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) >>> > > target_ulong pending = env->mip & env->mie & >>> > > ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); >>> > > target_ulong vspending = (env->mip & env->mie & >>> > > - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1; >>> > > + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); >>> > > >>> > > target_ulong mie = env->priv < PRV_M || >>> > > (env->priv == PRV_M && mstatus_mie); >>> > > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) >>> > > >>> > > if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && >>> > > !force_hs_execp) { >>> > > + /* >>> > > + * See if we need to adjust cause. Yes if its VS mode interrupt >>> > > + * no if hypervisor has delegated one of hs mode's interrupt >>> > > + */ >>> > > + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || >>> > > + cause == IRQ_VS_EXT) >>> > > + cause = cause - 1; >>> > > /* Trap to VS mode */ >>> > > } else if (riscv_cpu_virt_enabled(env)) { >>> > > /* Trap into HS mode, from virt */ >>> > > -- >>> > > 2.17.1 >>> > > >>> > > >>> >