From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751878AbdHABOW (ORCPT ); Mon, 31 Jul 2017 21:14:22 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:37243 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751327AbdHABOU (ORCPT ); Mon, 31 Jul 2017 21:14:20 -0400 Date: Mon, 31 Jul 2017 18:14:19 -0700 (PDT) X-Google-Original-Date: Mon, 31 Jul 2017 18:14:03 PDT (-0700) Subject: Re: [PATCH 05/17] clocksource: New RISC-V SBI timer driver In-Reply-To: <24a37ba4-df64-21c4-abec-18c0dbed0ab7@linaro.org> CC: yamada.masahiro@socionext.com, mmarek@suse.com, will.deacon@arm.com, peterz@infradead.org, boqun.feng@gmail.com, mingo@redhat.com, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, gregkh@linuxfoundation.org, jslaby@suse.com, davem@davemloft.net, mchehab@kernel.org, sfr@canb.auug.org.au, fweisbec@gmail.com, viro@zeniv.linux.org.uk, mcgrof@kernel.org, dledford@redhat.com, bart.vanassche@sandisk.com, sstabellini@kernel.org, daniel.vetter@ffwll.ch, mpe@ellerman.id.au, msalter@redhat.com, nicolas.dichtel@6wind.com, james.hogan@imgtec.com, paul.gortmaker@windriver.com, linux@roeck-us.net, heiko.carstens@de.ibm.com, schwidefsky@de.ibm.com, linux-kernel@vger.kernel.org, patches@groups.riscv.org, akpm@linux-foundation.org, albert@sifive.com From: Palmer Dabbelt To: daniel.lezcano@linaro.org Message-ID: Mime-Version: 1.0 (MHng) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Sorry, I missed this before submitting our v7. I'll respond properly in a bit... On Mon, 31 Jul 2017 04:00:26 PDT (-0700), daniel.lezcano@linaro.org wrote: > On 11/07/2017 03:39, Palmer Dabbelt wrote: >> The RISC-V ISA defines a per-hart real-time clock and timer, which is >> present on all systems. The clock is accessed via the 'rdtime' >> pseudo-instruction (which reads a CSR), and the timer is set via an SBI >> call. >> >> This driver attempts to split out the RISC-V ISA specific mechanisms of >> accessing the hardware from the clocksource driver by taking a pair of >> function pointers to issue the actual RISC-V specific instructions. >> >> Signed-off-by: Palmer Dabbelt >> --- > > [ ... ] > >> +#ifndef _LINUX_TIMER_RISCV_H >> +#define _LINUX_TIMER_RISCV_H >> + >> +/* >> + * All RISC-V systems have a timer attached to every hart. These timers can be >> + * read by the 'rdcycle' pseudo instruction, and can use the SBI to setup >> + * events. In order to abstract the architecture-specific timer reading and >> + * setting functions away from the clock event insertion code, we provide >> + * function pointers to the clockevent subsystem that perform two basic operations: >> + * rdtime() reads the timer on the current CPU, and next_event(delta) sets the >> + * next timer event to 'delta' cycles in the future. As the timers are >> + * inherently a per-cpu resource, these callbacks perform operations on the >> + * current hart. There is guaranteed to be exactly one timer per hart on all >> + * RISC-V systems. >> + */ > > Hi Palmer, > > The driver code must be self contained (eg. setup and irq handling). > > There are examples in the drivers/clocksource to stick on, for example > the jcore-pit.c or the mips-gic-timer.c drivers. > > I don't see the point to setup callbacks at init time. > > Thanks. > > -- Daniel > > >> +void timer_riscv_init(int cpu_id, >> + unsigned long riscv_timebase, >> + unsigned long long (*rdtime)(struct clocksource *), >> + int (*next_event)(unsigned long, struct clock_event_device *)); >> + >> +/* >> + * Looks up the clocksource or clock_even_device that cooresponds the given >> + * hart. >> + */ >> +struct clocksource *timer_riscv_source(int cpuid); >> +struct clock_event_device *timer_riscv_device(int cpu_id); >> + >> +#endif >>