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Fri, 12 Aug 2022 16:07:36 -0700 (PDT) Date: Fri, 12 Aug 2022 16:07:36 -0700 (PDT) X-Google-Original-Date: Fri, 12 Aug 2022 16:07:34 PDT (-0700) Subject: Re: [PATCH v2] RISC-V: Clean up the Zicbom block size probing In-Reply-To: CC: linux-riscv@lists.infradead.org, anup@brainfault.org, lkp@intel.com From: Palmer Dabbelt To: atishp@atishpatra.org Message-ID: Mime-Version: 1.0 (MHng) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220812_160740_914578_27336386 X-CRM114-Status: GOOD ( 27.76 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, 12 Aug 2022 10:43:02 PDT (-0700), atishp@atishpatra.org wrote: > On Fri, Aug 12, 2022 at 9:06 AM Palmer Dabbelt wrote: >> >> This fixes two issues: I truncated the warning's hart ID when porting to >> the 64-bit hart ID code, and the original code's warning handling could >> fire on an uninitialized hart ID. >> >> The biggest change here is that riscv_cbom_block_size is no longer >> initialized, as IMO the default isn't sane: there's nothing in the ISA >> that mandates any specific cache block size, so falling back to one will >> just silently produce the wrong answer on some systems. This also >> changes the probing order so the cache block size is known before >> enabling Zicbom support. >> >> Fixes: 3aefb2ee5bdd ("riscv: implement Zicbom-based CMO instructions + the t-head variant") >> Fixes: 1631ba1259d6 ("riscv: Add support for non-coherent devices using zicbom extension") >> Reported-by: kernel test robot >> Signed-off-by: Palmer Dabbelt >> >> --- >> >> Changes since v1 : >> >> * Everything but the unsigned long cbom_hartid. >> --- >> arch/riscv/kernel/setup.c | 2 +- >> arch/riscv/mm/dma-noncoherent.c | 22 ++++++++++++---------- >> 2 files changed, 13 insertions(+), 11 deletions(-) >> >> diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c >> index 95ef6e2bf45c..2dfc463b86bb 100644 >> --- a/arch/riscv/kernel/setup.c >> +++ b/arch/riscv/kernel/setup.c >> @@ -296,8 +296,8 @@ void __init setup_arch(char **cmdline_p) >> setup_smp(); >> #endif >> >> - riscv_fill_hwcap(); >> riscv_init_cbom_blocksize(); >> + riscv_fill_hwcap(); >> apply_boot_alternatives(); >> } >> >> diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c >> index cd2225304c82..3aa3572715d6 100644 >> --- a/arch/riscv/mm/dma-noncoherent.c >> +++ b/arch/riscv/mm/dma-noncoherent.c >> @@ -12,7 +12,7 @@ >> #include >> #include >> >> -static unsigned int riscv_cbom_block_size = L1_CACHE_BYTES; >> +static unsigned int riscv_cbom_block_size; > > What is the expected behavior if the block size is zero in CMO > operations ? As per my understanding, it will be equivalent to a nop. > Let me know if I am wrong. > > If that is the case, this is misleading as well. Maybe we should just > disable CMO extension altogether if it can't find the DT property. That seems reasonable to me, even if having a 0 block size is allowed by the spec it seems way more likely to have been a mistake. I'll send a v3, after puttting together a toolchain that actually builds this (assuming that's why I'm not getting the failures/warnings). > >> static bool noncoherent_supported; >> >> void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, >> @@ -80,37 +80,39 @@ void riscv_init_cbom_blocksize(void) >> { >> struct device_node *node; >> int ret; >> - u32 val; >> + u32 val, probed_block_size; >> >> + probed_block_size = 0; >> for_each_of_cpu_node(node) { >> - unsigned long hartid; >> - int cbom_hartid; >> + unsigned long hartid, cbom_hartid; >> >> ret = riscv_of_processor_hartid(node, &hartid); >> if (ret) >> continue; >> >> - if (hartid < 0) >> - continue; >> - >> /* set block-size for cbom extension if available */ >> ret = of_property_read_u32(node, "riscv,cbom-block-size", &val); >> if (ret) >> continue; >> >> - if (!riscv_cbom_block_size) { >> - riscv_cbom_block_size = val; >> + if (!probed_block_size) { >> + probed_block_size = val; >> cbom_hartid = hartid; >> } else { >> - if (riscv_cbom_block_size != val) >> + if (probed_block_size != val) >> pr_warn("cbom-block-size mismatched between harts %d and %lu\n", >> cbom_hartid, hartid); >> } >> } >> + >> + if (probed_block_size) >> + riscv_cbom_block_size = probed_block_size; >> } >> #endif >> >> void riscv_noncoherent_supported(void) >> { >> + WARN_ON(!riscv_cbom_block_size, >> + "Non-coherent DMA support enabled without a block size\n"); >> noncoherent_supported = true; >> } >> -- >> 2.34.1 >> >> >> _______________________________________________ >> linux-riscv mailing list >> linux-riscv@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv