From mboxrd@z Thu Jan 1 00:00:00 1970 From: Palmer Dabbelt Date: Mon, 11 Mar 2019 04:56:27 -0700 (PDT) Subject: [U-Boot] [PATCH v2 0/9] SMP support for RISC-V In-Reply-To: Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable To: u-boot@lists.denx.de On Thu, 07 Mar 2019 19:37:30 PST (-0800), Anup Patel wrote: >=20 >=20 >> -----Original Message----- >> From: Andreas Schwab >> Sent: Thursday, March 7, 2019 2:50 PM >> To: Anup Patel >> Cc: Atish Patra ; Anup Patel ; >> Auer, Lukas ; paul.walmsley at sifive.co= m; >> agraf at suse.de; u-boot at lists.denx.de; baruch at tkos.co.il; >> daniel.schwierzeck at gmail.com; bmeng.cn at gmail.com; >> rick at andestech.com; sr at denx.de; palmer at sifive.com >> Subject: Re: [PATCH v2 0/9] SMP support for RISC-V >>=20 >> On M=C3=A4r 07 2019, Anup Patel wrote: >>=20 >> > Like I mentioned, there is no functional issue with this series. The >> > warm-boot issues were fixed in OpenSBI. >> > >> > @Andreas, please try at your end. >>=20 >> As long as issue#65 isn't fixed opensbi is mostly a no-go for me. At le= ast it >> gives me more reasons to press the reset button. :-) >=20 > The reset button works fine for me an Atish. I am sure it works fine for = lot of > other folks too. >=20 > BTW, as-per discussion with SiFive folks the reset button on Unleashed > Board is not much tested and it can misbehave on certain boards. It is qu= ite > possible that you might have a "flaky" board. I don't think the reset button differs between boards. As far as I know, t= he=20 issues are really just that it doesn't reset everything -- specifically som= e of=20 the IP on the chip (clock, power, JTAG) isn't reset and nothing on the boar= d=20 (SD, ethernet, PCIe, etc) is reset. This frequently results in flakiness w= hen=20 debugging drivers, but the cores and memory system should all be OK. Is that issue 65 on github.com/opensbi? If so it clearly says this isn't a= =20 reset button issue.