Re: [PATCH] riscv: Correct SPARSEMEM configuration

From: Palmer Dabbelt <palmer@dabbelt.com>
To: wangkefeng.wang@huawei.com
Cc: linux-riscv@lists.infradead.org,
	Paul Walmsley <paul.walmsley@sifive.com>,
	 Atish Patra <Atish.Patra@wdc.com>,
	logang@deltatee.com, wangkefeng.wang@huawei.com
Subject: Re: [PATCH] riscv: Correct SPARSEMEM configuration
Date: Tue, 16 Mar 2021 22:10:14 -0700 (PDT)	[thread overview]
Message-ID: <mhng-afc9ae5d-ab12-4d65-81ea-1161eae50922@palmerdabbelt-glaptop> (raw)
In-Reply-To: <20210315120307.17142-1-wangkefeng.wang@huawei.com>

On Mon, 15 Mar 2021 05:03:07 PDT (-0700), wangkefeng.wang@huawei.com wrote:
> There are two issues for RV32,
> 1) if use FLATMEM, it is useless to enable SPARSEMEM_STATIC.
> 2) if use SPARSMEM, both SPARSEMEM_VMEMMAP and SPARSEMEM_STATIC is enabled.
>
> Fixes: d95f1a542c3d ("RISC-V: Implement sparsemem")
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
>  arch/riscv/Kconfig | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 85d626b8ce5e..87d7b52f278f 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -93,7 +93,6 @@ config RISCV
>  	select PCI_MSI if PCI
>  	select RISCV_INTC
>  	select RISCV_TIMER if RISCV_SBI
> -	select SPARSEMEM_STATIC if 32BIT
>  	select SPARSE_IRQ
>  	select SYSCTL_EXCEPTION_TRACE
>  	select THREAD_INFO_IN_TASK
> @@ -154,7 +153,8 @@ config ARCH_FLATMEM_ENABLE
>  config ARCH_SPARSEMEM_ENABLE
>  	def_bool y
>  	depends on MMU
> -	select SPARSEMEM_VMEMMAP_ENABLE
> +	select SPARSEMEM_STATIC if 32BIT && SPARSMEM
> +	select SPARSEMEM_VMEMMAP_ENABLE if 64BIT
>
>  config ARCH_SELECT_MEMORY_MODEL
>  	def_bool ARCH_SPARSEMEM_ENABLE

Thanks, this is on fixes.

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