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From: Palmer Dabbelt <palmer@dabbelt.com>
To: james.hogan@imgtec.com
Cc: Olof Johansson <olof@lixom.net>, Arnd Bergmann <arnd@arndb.de>,
	akpm@linux-foundation.org, albert@sifive.com,
	yamada.masahiro@socionext.com, mmarek@suse.com,
	will.deacon@arm.com, peterz@infradead.org, boqun.feng@gmail.com,
	mingo@redhat.com, daniel.lezcano@linaro.org, tglx@linutronix.de,
	jason@lakedaemon.net, marc.zyngier@arm.com,
	gregkh@linuxfoundation.org, jslaby@suse.com, davem@davemloft.net,
	mchehab@kernel.org, sfr@canb.auug.org.au, fweisbec@gmail.com,
	viro@zeniv.linux.org.uk, mcgrof@kernel.org, dledford@redhat.com,
	bart.vanassche@sandisk.com, sstabellini@kernel.org,
	daniel.vetter@ffwll.ch, mpe@ellerman.id.au, msalter@redhat.com,
	nicolas.dichtel@6wind.com, paul.gortmaker@windriver.com,
	linux@roeck-us.net, heiko.carstens@de.ibm.com,
	schwidefsky@de.ibm.com, linux-kernel@vger.kernel.org,
	patches@groups.riscv.org
Subject: Re: [PATCH 16/17] RISC-V: User-facing API
Date: Wed, 12 Jul 2017 09:24:24 -0700 (PDT)	[thread overview]
Message-ID: <mhng-b76d5b71-d337-499a-ba39-e86d4f0b739f@palmer-si-x1c4> (raw)
In-Reply-To: <20170712110751.GS6973@jhogan-linux.le.imgtec.org>

On Wed, 12 Jul 2017 04:07:51 PDT (-0700), james.hogan@imgtec.com wrote:
> On Tue, Jul 11, 2017 at 06:31:29PM -0700, Palmer Dabbelt wrote:
>> diff --git a/arch/riscv/include/asm/unistd.h b/arch/riscv/include/asm/unistd.h
>> new file mode 100644
>> index 000000000000..9f250ed007cd
>> --- /dev/null
>> +++ b/arch/riscv/include/asm/unistd.h
>> @@ -0,0 +1,16 @@
>> +/*
>> + * Copyright (C) 2012 Regents of the University of California
>> + *
>> + *   This program is free software; you can redistribute it and/or
>> + *   modify it under the terms of the GNU General Public License
>> + *   as published by the Free Software Foundation, version 2.
>> + *
>> + *   This program is distributed in the hope that it will be useful,
>> + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + *   GNU General Public License for more details.
>> + */
>> +
>> +#define __ARCH_HAVE_MMU
>> +#define __ARCH_WANT_SYS_CLONE
>> +#include <uapi/asm/unistd.h>
>
> It might be worth keeping arch/risc/include/uapi/asm/unistd.h around,
> even if it only includes asm-generic/unistd.h, as it'll only get added
> again the next time a syscall is deprecated from the default list in
> order to add the appropriate __ARCH_WANT_RENAMEAT-like define, but yeh
> no big deal.

That makes sense, but since it's gone I'll juts add it later -- I figure it's
always better to have less code when possible :).

>
>> diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
>> new file mode 100644
>> index 000000000000..ba3e80712797
>> --- /dev/null
>> +++ b/arch/riscv/kernel/ptrace.c
>> @@ -0,0 +1,125 @@
>
>> +static int riscv_gpr_get(struct task_struct *target,
>> +			 const struct user_regset *regset,
>> +			 unsigned int pos, unsigned int count,
>> +			 void *kbuf, void __user *ubuf)
>> +{
>> +	struct pt_regs *regs;
>> +
>> +	regs = task_pt_regs(target);
>> +	return user_regset_copyout(&pos, &count, &kbuf, &ubuf, regs, 0, -1);
>> +}
>> +
>> +static int riscv_gpr_set(struct task_struct *target,
>> +			 const struct user_regset *regset,
>> +			 unsigned int pos, unsigned int count,
>> +			 const void *kbuf, const void __user *ubuf)
>> +{
>> +	int ret;
>> +	struct pt_regs *regs;
>> +
>> +	regs = task_pt_regs(target);
>> +	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &regs, 0, -1);
>> +	return ret;
>> +}
>
> This is looking much safer now (the caller at least seems to always
> check pos + count is in range).
>
>> diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c
>> new file mode 100644
>> index 000000000000..e0a1b89583ef
>> --- /dev/null
>> +++ b/arch/riscv/kernel/signal.c
>> @@ -0,0 +1,289 @@
>
>> +static long setup_sigcontext(struct rt_sigframe __user *frame,
>> +	struct pt_regs *regs)
>> +{
>> +	struct sigcontext __user *sc = &frame->uc.uc_mcontext;
>> +	long err;
>> +	size_t i;
>> +	/* sc_regs is structured the same as the start of pt_regs */
>> +	err = __copy_to_user(&sc->sc_regs, regs, sizeof(sc->sc_regs));
>> +	/* Save the floating-point state. */
>> +	err |= save_d_state(regs, &sc->sc_fpregs.d);
>> +	/* We support no other extension state at this time. */
>> +	for (i = 0; i < ARRAY_SIZE(sc->sc_fpregs.q.reserved); i++)
>> +		err |= __put_user(0, &sc->sc_fpregs.q.reserved[i]);
>
> How should userland determine how to interpret sc_fpregs? It looks like
> you couldn't add f or q state without using one of these reserved
> fields, so why not just specify a field up front to say which fp format
> (if any) to interpret?

We considered that, but didn't want to tie ourserves to an extension mechanism
right now because we don't know what the vector extension is going to look
like.

> That would allow userland wanting to interpret it to safely check that
> field in a forward and backward compatible way without assuming a
> specific format is in use.

We set ELF_HWCAP (which percolates to userspace via the auxvec.  This contains
the entire set of extensions the kernel supports on the current machine, which
allows userspace to figure out what the format of the floating-point state is.

  reply	other threads:[~2017-07-12 16:24 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-12  1:31 RISC-V Linux Port v6 Palmer Dabbelt
2017-07-12  1:31 ` [PATCH 01/17] lib: Add shared copies of some GCC library routines Palmer Dabbelt
2017-07-12  1:31 ` [PATCH 02/17] pci: Add a generic, weakly-linked pcibios_align_resource Palmer Dabbelt
2017-07-12 13:41   ` Luis R. Rodriguez
2017-07-12 22:50   ` Bjorn Helgaas
2017-07-13 18:30     ` Palmer Dabbelt
2017-07-14  3:19   ` kbuild test robot
2017-07-12  1:31 ` [PATCH 03/17] pci: Add a generic, weakly-linked pcibios_fixup_bus Palmer Dabbelt
2017-07-12  1:31 ` [PATCH 04/17] MAINTAINERS: Add RISC-V Palmer Dabbelt
2017-07-12 11:16   ` James Hogan
2017-07-12 11:31     ` Arnd Bergmann
2017-07-12 14:51       ` [patches] " Jonathan Neuschäfer
2017-07-12  1:31 ` [PATCH 05/17] clocksource: New RISC-V SBI timer driver Palmer Dabbelt
2017-07-12  1:31 ` [PATCH 06/17] irqchip: RISC-V Local Interrupt Controller Driver Palmer Dabbelt
2017-07-12  1:31 ` [PATCH 07/17] irqchip: New RISC-V PLIC Driver Palmer Dabbelt
2017-07-12  1:31 ` [PATCH 08/17] tty: New RISC-V SBI console driver Palmer Dabbelt
2017-07-12  1:31 ` [PATCH 09/17] RISC-V: Init and Halt Code Palmer Dabbelt
2017-07-12  1:31 ` [PATCH 10/17] RISC-V: Atomic and Locking Code Palmer Dabbelt
2017-07-12 12:40   ` Boqun Feng
2017-07-12 12:44     ` Boqun Feng
2017-07-12 12:49     ` Peter Zijlstra
2017-07-12 17:17     ` Palmer Dabbelt
2017-07-12 13:13   ` Arnd Bergmann
2017-07-12  1:31 ` [PATCH 11/17] RISC-V: Generic library routines and assembly Palmer Dabbelt
2017-07-12  1:31 ` [PATCH 12/17] RISC-V: ELF and module implementation Palmer Dabbelt
2017-07-12  1:31 ` [PATCH 13/17] RISC-V: Task implementation Palmer Dabbelt
2017-07-12  1:31 ` [PATCH 14/17] RISC-V: Device, timer, IRQs, and the SBI Palmer Dabbelt
2017-07-12  1:31 ` [PATCH 15/17] RISC-V: Paging and MMU Palmer Dabbelt
2017-07-12  1:31 ` [PATCH 16/17] RISC-V: User-facing API Palmer Dabbelt
2017-07-12 11:07   ` James Hogan
2017-07-12 16:24     ` Palmer Dabbelt [this message]
2017-07-12 17:09       ` James Hogan
2017-07-13 21:50         ` Palmer Dabbelt
2017-07-12  1:31 ` [PATCH 17/17] RISC-V: Build Infastructure Palmer Dabbelt
2017-07-26  2:57   ` [patches] " Jonathan Neuschäfer
2017-07-26  5:20     ` Palmer Dabbelt
2017-07-26  6:52       ` Arnd Bergmann
2017-07-26 18:37       ` Jonathan Neuschäfer
2017-07-12  7:58 ` RISC-V Linux Port v6 Arnd Bergmann
2017-07-12 13:53   ` Luis R. Rodriguez
2017-07-12 17:55   ` Will Deacon
2017-07-12 19:34     ` Arnd Bergmann
  -- strict thread matches above, loose matches on Subject: below --
2017-07-11  1:39 RISC-V Linux Port v5 Palmer Dabbelt
2017-07-11  1:39 ` [PATCH 16/17] RISC-V: User-facing API Palmer Dabbelt
2017-07-11 13:39   ` Christoph Hellwig
2017-07-11 14:01     ` James Hogan

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