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Tue, 08 Oct 2019 11:53:32 -0700 (PDT) Date: Tue, 08 Oct 2019 11:53:32 -0700 (PDT) X-Google-Original-Date: Tue, 08 Oct 2019 11:39:34 PDT (-0700) Subject: Re: [PATCH v1 28/28] target/riscv: Allow enabling the Hypervisor extension In-Reply-To: <8dae4338c8938696dfcecee6e736f6b09cc82877.1566603412.git.alistair.francis@wdc.com> From: Palmer Dabbelt To: Alistair Francis Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.194 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Anup Patel , qemu-devel@nongnu.org, Atish Patra , Alistair Francis , alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, 23 Aug 2019 16:39:03 PDT (-0700), Alistair Francis wrote: > Signed-off-by: Alistair Francis > --- > target/riscv/cpu.c | 5 +++++ > target/riscv/cpu.h | 1 + > 2 files changed, 6 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 06ee551ebe..39e1c130df 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -447,6 +447,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > if (cpu->cfg.ext_u) { > target_misa |= RVU; > } > + if (cpu->cfg.ext_h) { > + target_misa |= RVH; > + } > > set_misa(env, RVXLEN | target_misa); > } > @@ -493,6 +496,8 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), > DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), > DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), > + /* This is experimental so mark with 'x-' */ > + DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), > DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index b63f1f3cdc..500496a3be 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -268,6 +268,7 @@ typedef struct RISCVCPU { > bool ext_c; > bool ext_s; > bool ext_u; > + bool ext_h; > bool ext_counters; > bool ext_ifencei; > bool ext_icsr; Reviewed-by: Palmer Dabbelt From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1iHuc8-0001P7-O4 for mharc-qemu-riscv@gnu.org; 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Tue, 08 Oct 2019 11:53:32 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id 22sm17454478pfo.131.2019.10.08.11.53.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2019 11:53:32 -0700 (PDT) Date: Tue, 08 Oct 2019 11:53:32 -0700 (PDT) X-Google-Original-Date: Tue, 08 Oct 2019 11:39:34 PDT (-0700) Subject: Re: [PATCH v1 28/28] target/riscv: Allow enabling the Hypervisor extension In-Reply-To: <8dae4338c8938696dfcecee6e736f6b09cc82877.1566603412.git.alistair.francis@wdc.com> CC: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Alistair Francis , alistair23@gmail.com, Atish Patra , Anup Patel From: Palmer Dabbelt To: Alistair Francis Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.196 X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 08 Oct 2019 18:53:38 -0000 On Fri, 23 Aug 2019 16:39:03 PDT (-0700), Alistair Francis wrote: > Signed-off-by: Alistair Francis > --- > target/riscv/cpu.c | 5 +++++ > target/riscv/cpu.h | 1 + > 2 files changed, 6 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 06ee551ebe..39e1c130df 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -447,6 +447,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > if (cpu->cfg.ext_u) { > target_misa |= RVU; > } > + if (cpu->cfg.ext_h) { > + target_misa |= RVH; > + } > > set_misa(env, RVXLEN | target_misa); > } > @@ -493,6 +496,8 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), > DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), > DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), > + /* This is experimental so mark with 'x-' */ > + DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), > DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index b63f1f3cdc..500496a3be 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -268,6 +268,7 @@ typedef struct RISCVCPU { > bool ext_c; > bool ext_s; > bool ext_u; > + bool ext_h; > bool ext_counters; > bool ext_ifencei; > bool ext_icsr; Reviewed-by: Palmer Dabbelt