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From: Palmer Dabbelt <palmer@dabbelt.com>
To: janwas@google.com
Cc: apatel@ventanamicro.com, malat@debian.org, atishp@atishpatra.org,
	linux-riscv@lists.infradead.org, aurelien@aurel32.net,
	Paul Walmsley <paul.walmsley@sifive.com>,
	jannewger@google.com
Subject: Re: rdcycle from userland with RISCV_PMU_SBI=y
Date: Wed, 28 Sep 2022 06:20:39 -0700 (PDT)	[thread overview]
Message-ID: <mhng-fb2905c4-7e33-483d-b223-020ae4501397@palmer-mbp2014> (raw)
In-Reply-To: <CAGRC-mhdmjcf=6gx8Rh5Rt8jvy5a2Rz+2g_UBRG_0fAG-D14uQ@mail.gmail.com>

[Sorry if this a mess, it's not showing up in my inbox.]

>> Currently, only "time" CSR is available to user-space and all other performance
>> counters should be enabled (or accessed) using Linux perf syscalls.
> Unfortunately that would seem to prevent precisely measuring very small code
> regions (order of 10 cycles). What is the corresponding advantage/benefit?
> As mentioned, there is no security gain from merely disabling rdcycle.
>
>> In the future, someone can always propose a RISC-V ISA extension to obfuscate
>> "time" CSR values visible to user-space but the "cycle" counter is
>> purely a performance counter and accurately reflects cycles taken by the CPU.
> Yes, this is why we use it. I'm curious why we think rdcycle is being
> used to measure wall time?
>
> About consistency: I understand there will be a time when rdcycle may
> or may not be available on Linux depending on PMU.
> But there is also bare metal, and other OSes. Is there a way for
> userland to detect whether rdcycle will fault?

We can't just trap rdcycle as SIGILL into userspace, it's part of the 
uABI.  I get the instruction was removed from the ISA, but that doesn't 
matter: we don't break userspace, regardless of how hard the ISA makes 
that.  

I understand there's some worries about the resolution of these counters 
on some systems, but the solution there is to maintain the uABI by 
trapping/emulating the removed instructions (and then providing some way 
for userspace to ask to turn that off, like we'll have to with a bunch 
of stuff).  That's a way's off, though, so for now we need to just stop 
breaking userspace.  There's also some proposals for sorting out the 
accuracy issues with ISA specs, but that's even farther off.

I just sent 
<https://lore.kernel.org/r/20220928131807.30386-1-palmer@rivosinc.com>, 
which hopefully fixes the issue.  I ended up with COVID so I'm kind of a 
mess, I can try to find some time to test it but it'd be much 
appreciated if someone who has a setup already can do so.

Sorry for the breakage.

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      reply	other threads:[~2022-09-28 13:20 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-01 21:15 rdcycle from userland with RISCV_PMU_SBI=y Aurelien Jarno
     [not found] ` <CAOnJCUJ-E-VyQOyh+psbJP4mDO9F+ShvnxDYjoCUUkH4rddJtw@mail.gmail.com>
     [not found]   ` <CAOnJCUKDQfCD7mh-RWrq0E8a3Fmp4Xz348THrS+SmJ71GX8=PA@mail.gmail.com>
2022-09-02  7:52     ` Mathieu Malaterre
2022-09-02  8:19       ` Anup Patel
     [not found]         ` <CAGRC-mj-v6RoGjCNr_TiabgqYX7H9mTXYE9tx6BhCKT5nHD-Aw@mail.gmail.com>
2022-09-02 10:31           ` Jan Wassenberg
2022-09-02 12:04           ` Anup Patel
2022-09-02 16:46             ` Aurelien Jarno
2022-09-05  5:40             ` Jan Wassenberg
2022-09-28 13:20               ` Palmer Dabbelt [this message]

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