Re: [patch V2 27/28] x86/speculation: Add seccomp Spectre v2 user space protection mode

From: Jiri Kosina <jikos@kernel.org>
To: Tim Chen <tim.c.chen@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Linux List Kernel Mailing <linux-kernel@vger.kernel.org>,
	the arch/x86 maintainers <x86@kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	Andrew Lutomirski <luto@kernel.org>,
	thomas.lendacky@amd.com, Josh Poimboeuf <jpoimboe@redhat.com>,
	Andrea Arcangeli <aarcange@redhat.com>,
	David Woodhouse <dwmw@amazon.co.uk>,
	Andi Kleen <ak@linux.intel.com>,
	dave.hansen@intel.com,
	Casey Schaufler <casey.schaufler@intel.com>,
	"Mallick, Asit K" <asit.k.mallick@intel.com>,
	"Van De Ven, Arjan" <arjan@linux.intel.com>,
	jcm@redhat.com, longman9394@gmail.com,
	Greg KH <gregkh@linuxfoundation.org>,
	david.c.stewart@intel.com, Kees Cook <keescook@chromium.org>,
	Jason Brandt <jason.w.brandt@intel.com>
Subject: Re: [patch V2 27/28] x86/speculation: Add seccomp Spectre v2 user space protection mode
Date: Tue, 4 Dec 2018 09:39:27 +0100 (CET)	[thread overview]
Message-ID: <nycvar.YFH.7.76.1812040937440.17216@cbobk.fhfr.pm> (raw)
In-Reply-To: <f4b903ef-828c-0b05-29c6-6f71677d120d@linux.intel.com>

On Mon, 3 Dec 2018, Tim Chen wrote:

> > Can we please just fix this stupid lie?
> > 
> > Yes, Intel calls it "STIBP" and tries to make it out to be about the
> > indirect branch predictor being per-SMT thread.
> > 
> > But the reason it is unacceptable is apparently because in reality it just
> > disables indirect branch prediction entirely. So yes, *technically* it's
> > true that that limits indirect branch prediction to just a single SMT
> > core, but in reality it is just a "go really slow" mode.
> > 
> > If STIBP had actually just keyed off the logical SMT thread, we wouldn't
> > need to have worried about it in the first place.
> > 
> > So let's document reality rather than Intel's Pollyanna world-view.
> > 
> > Reality matters. It's why we had to go all this. Lying about things
> > and making it appear like it's not a big deal was why the original
> > patch made it through without people noticing.
> > 
> 
> 
> To make the usage of STIBP and its working principles clear,
> here are some additional explanations of STIBP from our Intel
> HW architects.  This should also help answer some of the questions
> from Thomas and others on STIBP's usages with IBPB and IBRS.

Thanks a lot, this indeed does shed some light.

I have one question though:

[ ... snip ... ]
> On processors with enhanced IBRS support, we recommend setting IBRS to 1
> and left set. 

Then why doesn't CPU with EIBRS support acutally *default* to '1', with 
opt-out possibility for OS?

Thanks,

-- 
Jiri Kosina
SUSE Labs