From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (146.0.238.70:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 15 Jan 2019 12:02:02 -0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1gjNPr-0006Xj-TM for speck@linutronix.de; Tue, 15 Jan 2019 13:02:00 +0100 Received: from relay1.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id C2B9AAF14 for ; Tue, 15 Jan 2019 12:01:53 +0000 (UTC) Date: Tue, 15 Jan 2019 13:01:49 +0100 (CET) From: Jiri Kosina Subject: [MODERATED] Re: [PATCH v4 06/28] MDSv4 11 In-Reply-To: <892e7dbe-a531-539d-61f4-a723a40f0109@intel.com> Message-ID: References: =?utf-8?q?=3Ccover=2E1547256470=2Egit=2Eak=40linux=2Eintel?= =?utf-8?q?=2Ecom=3E=3C8388d491eac74581e40abe2096e81213037482be=2E1547?= =?utf-8?q?256470=2Egit=2Eak=40linux=2Eintel=2Ecom=3E?= <892e7dbe-a531-539d-61f4-a723a40f0109@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Mon, 14 Jan 2019, speck for Dave Hansen wrote: > > + case X86_BUG_MDS: > > + /* Assumes Hypervisor exposed HT state to us if in guest */ > > + if (boot_cpu_has(X86_FEATURE_MD_CLEAR)) { > > + if (cpu_smt_control !=3D CPU_SMT_ENABLED) > > + return sprintf(buf, "Mitigation: > > microcode\n"); > > + return sprintf(buf, "Mitigation: microcode, HT > > vulnerable\n"); > > + } > > + return sprintf(buf, "Vulnerable\n"); > > What are we trying to convey by saying "HT vulnerable"? There are a ton > of patches in this set that do HT mitigations, so just saying > "vulnerable" seems a bit cynical. If I read the code correctly, the only case where SMT is taken care of wrt. MDS is when one of the siblings is in idle (mwait/hlt). Other than that, SMT is pretty much uncovered if both threads are actually executing code AFAICS. -- Jiri Kosina SUSE Labs