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From: P J P <ppandit@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: niuguoxiang <niuguoxiang@huawei.com>,
	QEMU Developers <qemu-devel@nongnu.org>,
	qemu-arm <qemu-arm@nongnu.org>
Subject: Re: [Qemu-devel] 答复: [PATCH] intc: arm_gicv3: limit GICR ipriority index
Date: Wed, 6 Sep 2017 12:15:32 +0530 (IST)	[thread overview]
Message-ID: <nycvar.YSQ.7.76.1709061202500.13418@wniryva> (raw)
In-Reply-To: <CAFEAcA8JxuM-ddQVTBfgnSDD2fD+kz_RNShdNDqMqVH=zOKBfw@mail.gmail.com>

+-- On Tue, 5 Sep 2017, Peter Maydell wrote --+
| The code cannot be reached with a non-aligned value,
| because we register these functions via the gic_ops[]
| MemoryRegionops in hw/intc/arm_gicv3.c, and since we
| do not specify .valid.unaligned=true there, the memory.c
| code will throw out attempts at unaligned accesses.

  I see, thank you for the clarification; ie. within the range

   GICR_IPRIORITYR ... GICR_IPRIORITYR + 0x1f:

'offset' would be GICR_IPRIORITYR +0, +4, +8 ... 0x1c?

Maybe the patch could still be considered, not as bug fix though.

Thank you.
--
Prasad J Pandit / Red Hat Product Security Team
47AF CE69 3A90 54AA 9045 1053 DD13 3D32 FE5B 041F

      parent reply	other threads:[~2017-09-06  6:45 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-05 11:21 [Qemu-devel] [PATCH] intc: arm_gicv3: limit GICR ipriority index P J P
2017-09-05 11:58 ` Peter Maydell
2017-09-05 12:29   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-09-05 12:30   ` [Qemu-devel] 答复: " niuguoxiang
2017-09-05 12:35     ` Peter Maydell
2017-09-05 19:42       ` Eric Blake
2017-09-06  6:45       ` P J P [this message]

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