* [PATCH v4 1/7] drm/i915: Correctly handle error path in i915_gem_init_hw
@ 2018-03-23 15:14 Michal Wajdeczko
2018-03-23 15:14 ` [PATCH v4 2/7] drm/i915/uc: Disable GuC submission during sanitize Michal Wajdeczko
` (8 more replies)
0 siblings, 9 replies; 14+ messages in thread
From: Michal Wajdeczko @ 2018-03-23 15:14 UTC (permalink / raw)
To: intel-gfx
In function gem_init_hw() we are calling uc_init_hw() but in case
of error later in function, we missed to call matching uc_fini_hw()
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 802df8e..7fad180 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5171,9 +5171,15 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
/* Only when the HW is re-initialised, can we replay the requests */
ret = __i915_gem_restart_engines(dev_priv);
+ if (ret)
+ goto cleanup_uc;
out:
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
return ret;
+
+cleanup_uc:
+ intel_uc_fini_hw(dev_priv);
+ goto out;
}
static int __intel_engines_record_defaults(struct drm_i915_private *i915)
--
1.9.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v4 2/7] drm/i915/uc: Disable GuC submission during sanitize
2018-03-23 15:14 [PATCH v4 1/7] drm/i915: Correctly handle error path in i915_gem_init_hw Michal Wajdeczko
@ 2018-03-23 15:14 ` Michal Wajdeczko
2018-03-26 10:36 ` Sagar Arun Kamble
2018-03-23 15:14 ` [PATCH v4 3/7] drm/i915/uc: Fully sanitize uC in uc_fini_hw Michal Wajdeczko
` (7 subsequent siblings)
8 siblings, 1 reply; 14+ messages in thread
From: Michal Wajdeczko @ 2018-03-23 15:14 UTC (permalink / raw)
To: intel-gfx
We should not leave GuC submission enabled after sanitize,
as we are going to reset all GuC/HuC hardware.
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_uc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 34f8a2c..2389828 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -331,6 +331,9 @@ void intel_uc_sanitize(struct drm_i915_private *i915)
GEM_BUG_ON(!HAS_GUC(i915));
+ if (USES_GUC_SUBMISSION(dev_priv))
+ intel_guc_submission_disable(guc);
+
guc_disable_communication(guc);
intel_huc_sanitize(huc);
--
1.9.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v4 3/7] drm/i915/uc: Fully sanitize uC in uc_fini_hw
2018-03-23 15:14 [PATCH v4 1/7] drm/i915: Correctly handle error path in i915_gem_init_hw Michal Wajdeczko
2018-03-23 15:14 ` [PATCH v4 2/7] drm/i915/uc: Disable GuC submission during sanitize Michal Wajdeczko
@ 2018-03-23 15:14 ` Michal Wajdeczko
2018-03-26 11:23 ` Sagar Arun Kamble
2018-03-23 15:14 ` [PATCH v4 4/7] drm/i915/uc: Use correct error code for GuC initialization failure Michal Wajdeczko
` (6 subsequent siblings)
8 siblings, 1 reply; 14+ messages in thread
From: Michal Wajdeczko @ 2018-03-23 15:14 UTC (permalink / raw)
To: intel-gfx
Today uc_fini_hw is subset of uc_sanitize, but remaining
code in sanitize function is also desired for uc_fini_hw.
Instead of duplicating the code, just call uc_sanitize,
but leave as separate function to maintain symmetry with
uc_init_hw.
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_uc.c | 14 ++------------
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 2389828..9ff0c5a 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -434,19 +434,9 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
return ret;
}
-void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
+void intel_uc_fini_hw(struct drm_i915_private *i915)
{
- struct intel_guc *guc = &dev_priv->guc;
-
- if (!USES_GUC(dev_priv))
- return;
-
- GEM_BUG_ON(!HAS_GUC(dev_priv));
-
- if (USES_GUC_SUBMISSION(dev_priv))
- intel_guc_submission_disable(guc);
-
- guc_disable_communication(guc);
+ intel_uc_sanitize(i915);
}
int intel_uc_suspend(struct drm_i915_private *i915)
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v4 4/7] drm/i915/uc: Use correct error code for GuC initialization failure
2018-03-23 15:14 [PATCH v4 1/7] drm/i915: Correctly handle error path in i915_gem_init_hw Michal Wajdeczko
2018-03-23 15:14 ` [PATCH v4 2/7] drm/i915/uc: Disable GuC submission during sanitize Michal Wajdeczko
2018-03-23 15:14 ` [PATCH v4 3/7] drm/i915/uc: Fully sanitize uC in uc_fini_hw Michal Wajdeczko
@ 2018-03-23 15:14 ` Michal Wajdeczko
2018-03-23 15:14 ` [PATCH v4 5/7] drm/i915/uc: Use helper functions to detect fw load status Michal Wajdeczko
` (5 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Michal Wajdeczko @ 2018-03-23 15:14 UTC (permalink / raw)
To: intel-gfx
Since commit 6ca9a2beb54a ("drm/i915: Unwind i915_gem_init() failure")
we believed that we correctly handle all errors encountered during
GuC initialization, including special one that indicates request to
run driver with disabled GPU submission (-EIO).
Unfortunately since commit 121981fafe69 ("drm/i915/guc: Combine
enable_guc_loading|submission modparams") we stopped using that
error code to avoid unwanted fallback to execlist submission mode.
In result any GuC initialization failure was treated as non-recoverable
error leading to driver load abort, so we could not even read related
GuC error log to investigate cause of the problem.
Fix that by always returning -EIO on uC hardware related failure.
v2: don't allow -EIO from uc_init
don't call uc_fini[_misc] on -EIO
mark guc fw as failed on hw init failure
prepare uc_fini_hw to run after earlier -EIO
v3: update comments (Sagar)
use sanitize functions on failure in init_hw (Michal)
and also sanitize guc/huc fw in fini_hw (Michal)
v4: rebase
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michal Winiarski <michal.winiarski@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/i915_gem.c | 17 ++++++++++-------
drivers/gpu/drm/i915/intel_guc.h | 5 +++++
drivers/gpu/drm/i915/intel_uc.c | 17 +++++++++++++----
drivers/gpu/drm/i915/intel_uc_fw.h | 5 +++++
4 files changed, 33 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7fad180..9b13b3e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5361,8 +5361,10 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
intel_init_gt_powersave(dev_priv);
ret = intel_uc_init(dev_priv);
- if (ret)
+ if (ret) {
+ GEM_BUG_ON(ret == -EIO);
goto err_pm;
+ }
ret = i915_gem_init_hw(dev_priv);
if (ret)
@@ -5409,7 +5411,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
i915_gem_contexts_lost(dev_priv);
intel_uc_fini_hw(dev_priv);
err_uc_init:
- intel_uc_fini(dev_priv);
+ if (ret != -EIO)
+ intel_uc_fini(dev_priv);
err_pm:
if (ret != -EIO) {
intel_cleanup_gt_powersave(dev_priv);
@@ -5423,15 +5426,15 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
mutex_unlock(&dev_priv->drm.struct_mutex);
- intel_uc_fini_misc(dev_priv);
-
- if (ret != -EIO)
+ if (ret != -EIO) {
+ intel_uc_fini_misc(dev_priv);
i915_gem_cleanup_userptr(dev_priv);
+ }
if (ret == -EIO) {
/*
- * Allow engine initialisation to fail by marking the GPU as
- * wedged. But we only want to do this where the GPU is angry,
+ * Allow engines or uC initialization to fail by marking the GPU
+ * as wedged. But we only want to do this when the GPU is angry,
* for all other failure, such as an allocation failure, bail.
*/
if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 13f3d1d..7325b0e 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -155,6 +155,11 @@ static inline int intel_guc_sanitize(struct intel_guc *guc)
return 0;
}
+static inline bool intel_guc_is_loaded(struct intel_guc *guc)
+{
+ return intel_uc_fw_is_loaded(&guc->fw);
+}
+
static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask)
{
spin_lock_irq(&guc->irq_lock);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 9ff0c5a..fad9dde 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -427,15 +427,24 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
* Note that there is no fallback as either user explicitly asked for
* the GuC or driver default option was to run with the GuC enabled.
*/
- if (GEM_WARN_ON(ret == -EIO))
- ret = -EINVAL;
-
dev_err(dev_priv->drm.dev, "GuC initialization failed %d\n", ret);
- return ret;
+
+ /* Sanitize GuC/HuC to avoid clean-up on wedged */
+ intel_huc_sanitize(huc);
+ intel_guc_sanitize(guc);
+ GEM_BUG_ON(intel_guc_is_loaded(guc));
+
+ /* We want to disable GPU submission but keep KMS alive */
+ return -EIO;
}
void intel_uc_fini_hw(struct drm_i915_private *i915)
{
+ struct intel_guc *guc = &i915->guc;
+
+ if (!intel_guc_is_loaded(guc))
+ return;
+
intel_uc_sanitize(i915);
}
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h b/drivers/gpu/drm/i915/intel_uc_fw.h
index dc33b12..77ad2aa 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.h
+++ b/drivers/gpu/drm/i915/intel_uc_fw.h
@@ -121,6 +121,11 @@ static inline void intel_uc_fw_sanitize(struct intel_uc_fw *uc_fw)
uc_fw->load_status = INTEL_UC_FIRMWARE_PENDING;
}
+static inline bool intel_uc_fw_is_loaded(struct intel_uc_fw *uc_fw)
+{
+ return uc_fw->load_status == INTEL_UC_FIRMWARE_SUCCESS;
+}
+
/**
* intel_uc_fw_get_upload_size() - Get size of firmware needed to be uploaded.
* @uc_fw: uC firmware.
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v4 5/7] drm/i915/uc: Use helper functions to detect fw load status
2018-03-23 15:14 [PATCH v4 1/7] drm/i915: Correctly handle error path in i915_gem_init_hw Michal Wajdeczko
` (2 preceding siblings ...)
2018-03-23 15:14 ` [PATCH v4 4/7] drm/i915/uc: Use correct error code for GuC initialization failure Michal Wajdeczko
@ 2018-03-23 15:14 ` Michal Wajdeczko
2018-03-23 15:14 ` [PATCH v4 6/7] drm/i915/uc: Trivial s/dev_priv/i915 in intel_uc.c Michal Wajdeczko
` (4 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Michal Wajdeczko @ 2018-03-23 15:14 UTC (permalink / raw)
To: intel-gfx
We don't have to check load status values.
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/intel_huc.c | 2 +-
drivers/gpu/drm/i915/intel_uc.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 2912852..975ae61 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -51,7 +51,7 @@ int intel_huc_auth(struct intel_huc *huc)
u32 status;
int ret;
- if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
+ if (!intel_uc_fw_is_loaded(&huc->fw))
return -ENOEXEC;
vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index fad9dde..d1ec948 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -456,7 +456,7 @@ int intel_uc_suspend(struct drm_i915_private *i915)
if (!USES_GUC(i915))
return 0;
- if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
+ if (!intel_guc_is_loaded(guc))
return 0;
err = intel_guc_suspend(guc);
@@ -478,7 +478,7 @@ int intel_uc_resume(struct drm_i915_private *i915)
if (!USES_GUC(i915))
return 0;
- if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
+ if (!intel_guc_is_loaded(guc))
return 0;
if (i915_modparams.guc_log_level)
--
1.9.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v4 6/7] drm/i915/uc: Trivial s/dev_priv/i915 in intel_uc.c
2018-03-23 15:14 [PATCH v4 1/7] drm/i915: Correctly handle error path in i915_gem_init_hw Michal Wajdeczko
` (3 preceding siblings ...)
2018-03-23 15:14 ` [PATCH v4 5/7] drm/i915/uc: Use helper functions to detect fw load status Michal Wajdeczko
@ 2018-03-23 15:14 ` Michal Wajdeczko
2018-03-23 15:14 ` [PATCH v4 7/7] HAX: Enable GuC for CI Michal Wajdeczko
` (3 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Michal Wajdeczko @ 2018-03-23 15:14 UTC (permalink / raw)
To: intel-gfx
Some functions already use i915 name instead of dev_priv.
Let's rename this param in all remaining functions, except
those that still use legacy macros.
v2: don't forget about function descriptions (Sagar)
v3: rebased
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/intel_uc.c | 115 ++++++++++++++++++++--------------------
1 file changed, 57 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index d1ec948..e077c01 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -50,10 +50,10 @@ static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv)
return ret;
}
-static int __get_platform_enable_guc(struct drm_i915_private *dev_priv)
+static int __get_platform_enable_guc(struct drm_i915_private *i915)
{
- struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
- struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
+ struct intel_uc_fw *guc_fw = &i915->guc.fw;
+ struct intel_uc_fw *huc_fw = &i915->huc.fw;
int enable_guc = 0;
/* Default is to enable GuC/HuC if we know their firmwares */
@@ -67,11 +67,11 @@ static int __get_platform_enable_guc(struct drm_i915_private *dev_priv)
return enable_guc;
}
-static int __get_default_guc_log_level(struct drm_i915_private *dev_priv)
+static int __get_default_guc_log_level(struct drm_i915_private *i915)
{
int guc_log_level;
- if (!HAS_GUC(dev_priv) || !intel_uc_is_using_guc())
+ if (!HAS_GUC(i915) || !intel_uc_is_using_guc())
guc_log_level = GUC_LOG_LEVEL_DISABLED;
else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
@@ -86,7 +86,7 @@ static int __get_default_guc_log_level(struct drm_i915_private *dev_priv)
/**
* sanitize_options_early - sanitize uC related modparam options
- * @dev_priv: device private
+ * @i915: device private
*
* In case of "enable_guc" option this function will attempt to modify
* it only if it was initially set to "auto(-1)". Default value for this
@@ -101,14 +101,14 @@ static int __get_default_guc_log_level(struct drm_i915_private *dev_priv)
* unless GuC is enabled on given platform and the driver is compiled with
* debug config when this modparam will default to "enable(1..4)".
*/
-static void sanitize_options_early(struct drm_i915_private *dev_priv)
+static void sanitize_options_early(struct drm_i915_private *i915)
{
- struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
- struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
+ struct intel_uc_fw *guc_fw = &i915->guc.fw;
+ struct intel_uc_fw *huc_fw = &i915->huc.fw;
/* A negative value means "use platform default" */
if (i915_modparams.enable_guc < 0)
- i915_modparams.enable_guc = __get_platform_enable_guc(dev_priv);
+ i915_modparams.enable_guc = __get_platform_enable_guc(i915);
DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s)\n",
i915_modparams.enable_guc,
@@ -119,28 +119,28 @@ static void sanitize_options_early(struct drm_i915_private *dev_priv)
if (intel_uc_is_using_guc() && !intel_uc_fw_is_selected(guc_fw)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
"enable_guc", i915_modparams.enable_guc,
- !HAS_GUC(dev_priv) ? "no GuC hardware" :
- "no GuC firmware");
+ !HAS_GUC(i915) ? "no GuC hardware" :
+ "no GuC firmware");
}
/* Verify HuC firmware availability */
if (intel_uc_is_using_huc() && !intel_uc_fw_is_selected(huc_fw)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
"enable_guc", i915_modparams.enable_guc,
- !HAS_HUC(dev_priv) ? "no HuC hardware" :
- "no HuC firmware");
+ !HAS_HUC(i915) ? "no HuC hardware" :
+ "no HuC firmware");
}
/* A negative value means "use platform/config default" */
if (i915_modparams.guc_log_level < 0)
i915_modparams.guc_log_level =
- __get_default_guc_log_level(dev_priv);
+ __get_default_guc_log_level(i915);
if (i915_modparams.guc_log_level > 0 && !intel_uc_is_using_guc()) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
"guc_log_level", i915_modparams.guc_log_level,
- !HAS_GUC(dev_priv) ? "no GuC hardware" :
- "GuC not enabled");
+ !HAS_GUC(i915) ? "no GuC hardware" :
+ "GuC not enabled");
i915_modparams.guc_log_level = 0;
}
@@ -162,49 +162,48 @@ static void sanitize_options_early(struct drm_i915_private *dev_priv)
GEM_BUG_ON(i915_modparams.guc_log_level < 0);
}
-void intel_uc_init_early(struct drm_i915_private *dev_priv)
+void intel_uc_init_early(struct drm_i915_private *i915)
{
- intel_guc_init_early(&dev_priv->guc);
- intel_huc_init_early(&dev_priv->huc);
+ intel_guc_init_early(&i915->guc);
+ intel_huc_init_early(&i915->huc);
- sanitize_options_early(dev_priv);
+ sanitize_options_early(i915);
}
-void intel_uc_init_fw(struct drm_i915_private *dev_priv)
+void intel_uc_init_fw(struct drm_i915_private *i915)
{
- if (!USES_GUC(dev_priv))
+ if (!USES_GUC(i915))
return;
- if (USES_HUC(dev_priv))
- intel_uc_fw_fetch(dev_priv, &dev_priv->huc.fw);
+ if (USES_HUC(i915))
+ intel_uc_fw_fetch(i915, &i915->huc.fw);
- intel_uc_fw_fetch(dev_priv, &dev_priv->guc.fw);
+ intel_uc_fw_fetch(i915, &i915->guc.fw);
}
-void intel_uc_fini_fw(struct drm_i915_private *dev_priv)
+void intel_uc_fini_fw(struct drm_i915_private *i915)
{
- if (!USES_GUC(dev_priv))
+ if (!USES_GUC(i915))
return;
- intel_uc_fw_fini(&dev_priv->guc.fw);
+ intel_uc_fw_fini(&i915->guc.fw);
- if (USES_HUC(dev_priv))
- intel_uc_fw_fini(&dev_priv->huc.fw);
+ if (USES_HUC(i915))
+ intel_uc_fw_fini(&i915->huc.fw);
- guc_free_load_err_log(&dev_priv->guc);
+ guc_free_load_err_log(&i915->guc);
}
/**
* intel_uc_init_mmio - setup uC MMIO access
- *
- * @dev_priv: device private
+ * @i915: device private
*
* Setup minimal state necessary for MMIO accesses later in the
* initialization sequence.
*/
-void intel_uc_init_mmio(struct drm_i915_private *dev_priv)
+void intel_uc_init_mmio(struct drm_i915_private *i915)
{
- intel_guc_init_send_regs(&dev_priv->guc);
+ intel_guc_init_send_regs(&i915->guc);
}
static void guc_capture_load_err_log(struct intel_guc *guc)
@@ -226,11 +225,11 @@ static void guc_free_load_err_log(struct intel_guc *guc)
static int guc_enable_communication(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_private *i915 = guc_to_i915(guc);
- gen9_enable_guc_interrupts(dev_priv);
+ gen9_enable_guc_interrupts(i915);
- if (HAS_GUC_CT(dev_priv))
+ if (HAS_GUC_CT(i915))
return intel_guc_ct_enable(&guc->ct);
guc->send = intel_guc_send_mmio;
@@ -239,22 +238,22 @@ static int guc_enable_communication(struct intel_guc *guc)
static void guc_disable_communication(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_private *i915 = guc_to_i915(guc);
- if (HAS_GUC_CT(dev_priv))
+ if (HAS_GUC_CT(i915))
intel_guc_ct_disable(&guc->ct);
- gen9_disable_guc_interrupts(dev_priv);
+ gen9_disable_guc_interrupts(i915);
guc->send = intel_guc_send_nop;
}
-int intel_uc_init_misc(struct drm_i915_private *dev_priv)
+int intel_uc_init_misc(struct drm_i915_private *i915)
{
- struct intel_guc *guc = &dev_priv->guc;
+ struct intel_guc *guc = &i915->guc;
int ret;
- if (!USES_GUC(dev_priv))
+ if (!USES_GUC(i915))
return 0;
intel_guc_init_ggtt_pin_bias(guc);
@@ -266,32 +265,32 @@ int intel_uc_init_misc(struct drm_i915_private *dev_priv)
return 0;
}
-void intel_uc_fini_misc(struct drm_i915_private *dev_priv)
+void intel_uc_fini_misc(struct drm_i915_private *i915)
{
- struct intel_guc *guc = &dev_priv->guc;
+ struct intel_guc *guc = &i915->guc;
- if (!USES_GUC(dev_priv))
+ if (!USES_GUC(i915))
return;
intel_guc_fini_wq(guc);
}
-int intel_uc_init(struct drm_i915_private *dev_priv)
+int intel_uc_init(struct drm_i915_private *i915)
{
- struct intel_guc *guc = &dev_priv->guc;
+ struct intel_guc *guc = &i915->guc;
int ret;
- if (!USES_GUC(dev_priv))
+ if (!USES_GUC(i915))
return 0;
- if (!HAS_GUC(dev_priv))
+ if (!HAS_GUC(i915))
return -ENODEV;
ret = intel_guc_init(guc);
if (ret)
return ret;
- if (USES_GUC_SUBMISSION(dev_priv)) {
+ if (USES_GUC_SUBMISSION(i915)) {
/*
* This is stuff we need to have available at fw load time
* if we are planning to enable submission later
@@ -306,16 +305,16 @@ int intel_uc_init(struct drm_i915_private *dev_priv)
return 0;
}
-void intel_uc_fini(struct drm_i915_private *dev_priv)
+void intel_uc_fini(struct drm_i915_private *i915)
{
- struct intel_guc *guc = &dev_priv->guc;
+ struct intel_guc *guc = &i915->guc;
- if (!USES_GUC(dev_priv))
+ if (!USES_GUC(i915))
return;
- GEM_BUG_ON(!HAS_GUC(dev_priv));
+ GEM_BUG_ON(!HAS_GUC(i915));
- if (USES_GUC_SUBMISSION(dev_priv))
+ if (USES_GUC_SUBMISSION(i915))
intel_guc_submission_fini(guc);
intel_guc_fini(guc);
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v4 7/7] HAX: Enable GuC for CI
2018-03-23 15:14 [PATCH v4 1/7] drm/i915: Correctly handle error path in i915_gem_init_hw Michal Wajdeczko
` (4 preceding siblings ...)
2018-03-23 15:14 ` [PATCH v4 6/7] drm/i915/uc: Trivial s/dev_priv/i915 in intel_uc.c Michal Wajdeczko
@ 2018-03-23 15:14 ` Michal Wajdeczko
2018-03-23 17:18 ` ✓ Fi.CI.BAT: success for series starting with [v4,1/7] drm/i915: Correctly handle error path in i915_gem_init_hw Patchwork
` (2 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Michal Wajdeczko @ 2018-03-23 15:14 UTC (permalink / raw)
To: intel-gfx
v2: except running with HYPERVISOR
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index c963603..53037b5 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
- param(int, enable_guc, 0) \
+ param(int, enable_guc, -1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index e077c01..ce44299 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -63,6 +63,8 @@ static int __get_platform_enable_guc(struct drm_i915_private *i915)
enable_guc |= ENABLE_GUC_LOAD_HUC;
/* Any platform specific fine-tuning can be done here */
+ if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
+ enable_guc = 0;
return enable_guc;
}
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [v4,1/7] drm/i915: Correctly handle error path in i915_gem_init_hw
2018-03-23 15:14 [PATCH v4 1/7] drm/i915: Correctly handle error path in i915_gem_init_hw Michal Wajdeczko
` (5 preceding siblings ...)
2018-03-23 15:14 ` [PATCH v4 7/7] HAX: Enable GuC for CI Michal Wajdeczko
@ 2018-03-23 17:18 ` Patchwork
2018-03-23 20:15 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-03-26 10:16 ` [PATCH v4 1/7] " Sagar Arun Kamble
8 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2018-03-23 17:18 UTC (permalink / raw)
To: Michal Wajdeczko; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v4,1/7] drm/i915: Correctly handle error path in i915_gem_init_hw
URL : https://patchwork.freedesktop.org/series/40581/
State : success
== Summary ==
Series 40581v1 series starting with [v4,1/7] drm/i915: Correctly handle error path in i915_gem_init_hw
https://patchwork.freedesktop.org/api/1.0/series/40581/revisions/1/mbox/
---- Possible new issues:
Test kms_flip:
Subgroup basic-flip-vs-dpms:
incomplete -> PASS (fi-bxt-dsi)
---- Known issues:
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail -> PASS (fi-gdg-551) fdo#102575
Test kms_chamelium:
Subgroup hdmi-hpd-fast:
skip -> FAIL (fi-kbl-7500u) fdo#102672
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
notrun -> INCOMPLETE (fi-bxt-dsi) fdo#103927
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fi-bdw-5557u total:285 pass:264 dwarn:0 dfail:0 fail:0 skip:21 time:437s
fi-bdw-gvtdvm total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:442s
fi-blb-e6850 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:383s
fi-bsw-n3050 total:285 pass:239 dwarn:0 dfail:0 fail:0 skip:46 time:542s
fi-bwr-2160 total:285 pass:180 dwarn:0 dfail:0 fail:0 skip:105 time:296s
fi-bxt-dsi total:243 pass:216 dwarn:0 dfail:0 fail:0 skip:26
fi-bxt-j4205 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:513s
fi-byt-j1900 total:285 pass:250 dwarn:0 dfail:0 fail:0 skip:35 time:518s
fi-byt-n2820 total:285 pass:246 dwarn:0 dfail:0 fail:0 skip:39 time:507s
fi-cfl-8700k total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:414s
fi-cfl-u total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:511s
fi-cnl-y3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:594s
fi-elk-e7500 total:285 pass:225 dwarn:1 dfail:0 fail:0 skip:59 time:425s
fi-gdg-551 total:285 pass:177 dwarn:0 dfail:0 fail:0 skip:108 time:317s
fi-glk-1 total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:534s
fi-hsw-4770 total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:403s
fi-ilk-650 total:285 pass:225 dwarn:0 dfail:0 fail:0 skip:60 time:417s
fi-ivb-3520m total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:479s
fi-ivb-3770 total:285 pass:252 dwarn:0 dfail:0 fail:0 skip:33 time:429s
fi-kbl-7500u total:285 pass:260 dwarn:1 dfail:0 fail:1 skip:23 time:472s
fi-kbl-7567u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:465s
fi-kbl-r total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:513s
fi-pnv-d510 total:285 pass:219 dwarn:1 dfail:0 fail:0 skip:65 time:654s
fi-skl-6260u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:441s
fi-skl-6600u total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:531s
fi-skl-6700k2 total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:509s
fi-skl-6770hq total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:509s
fi-skl-guc total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:430s
fi-skl-gvtdvm total:285 pass:262 dwarn:0 dfail:0 fail:0 skip:23 time:444s
fi-snb-2520m total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:585s
fi-snb-2600 total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:400s
Blacklisted hosts:
fi-cfl-s3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:571s
fi-cnl-psr total:224 pass:198 dwarn:0 dfail:0 fail:1 skip:24
fi-glk-j4005 total:285 pass:255 dwarn:0 dfail:0 fail:0 skip:30 time:488s
157295bdb3516bc0972daffcef016d668f549d79 drm-tip: 2018y-03m-23d-15h-22m-25s UTC integration manifest
653493dcfa8b HAX: Enable GuC for CI
639d7f861507 drm/i915/uc: Trivial s/dev_priv/i915 in intel_uc.c
cd87bb6e6ca0 drm/i915/uc: Use helper functions to detect fw load status
39a65016b155 drm/i915/uc: Use correct error code for GuC initialization failure
9c41fdcd25fa drm/i915/uc: Fully sanitize uC in uc_fini_hw
2b1c9abb7c6c drm/i915/uc: Disable GuC submission during sanitize
8e01292d7b9b drm/i915: Correctly handle error path in i915_gem_init_hw
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8477/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✗ Fi.CI.IGT: failure for series starting with [v4,1/7] drm/i915: Correctly handle error path in i915_gem_init_hw
2018-03-23 15:14 [PATCH v4 1/7] drm/i915: Correctly handle error path in i915_gem_init_hw Michal Wajdeczko
` (6 preceding siblings ...)
2018-03-23 17:18 ` ✓ Fi.CI.BAT: success for series starting with [v4,1/7] drm/i915: Correctly handle error path in i915_gem_init_hw Patchwork
@ 2018-03-23 20:15 ` Patchwork
2018-03-26 10:16 ` [PATCH v4 1/7] " Sagar Arun Kamble
8 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2018-03-23 20:15 UTC (permalink / raw)
To: Michal Wajdeczko; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v4,1/7] drm/i915: Correctly handle error path in i915_gem_init_hw
URL : https://patchwork.freedesktop.org/series/40581/
State : failure
== Summary ==
---- Possible new issues:
Test drm_mm:
Subgroup sanitycheck:
pass -> INCOMPLETE (shard-apl)
Test drv_selftest:
Subgroup live_guc:
pass -> SKIP (shard-apl)
Subgroup live_hangcheck:
pass -> DMESG-FAIL (shard-apl)
Test gem_eio:
Subgroup execbuf:
pass -> INCOMPLETE (shard-apl)
Subgroup in-flight:
pass -> INCOMPLETE (shard-apl)
Subgroup in-flight-contexts:
pass -> INCOMPLETE (shard-apl)
Subgroup wait:
pass -> INCOMPLETE (shard-apl)
Test gem_mmap_gtt:
Subgroup hang:
pass -> INCOMPLETE (shard-apl)
Test gem_mocs_settings:
Subgroup mocs-reset-ctx-render:
pass -> INCOMPLETE (shard-apl)
Subgroup mocs-reset-dirty-render:
pass -> INCOMPLETE (shard-apl)
Subgroup mocs-reset-render:
pass -> INCOMPLETE (shard-apl)
Test kms_flip:
Subgroup flip-vs-panning-vs-hang:
pass -> INCOMPLETE (shard-apl)
Test kms_vblank:
Subgroup pipe-a-ts-continuation-modeset-hang:
pass -> INCOMPLETE (shard-apl)
Subgroup pipe-a-wait-idle-hang:
pass -> INCOMPLETE (shard-apl)
Subgroup pipe-b-query-busy-hang:
pass -> INCOMPLETE (shard-apl)
Subgroup pipe-b-ts-continuation-modeset-hang:
pass -> INCOMPLETE (shard-apl)
Subgroup pipe-b-wait-busy-hang:
pass -> INCOMPLETE (shard-apl)
Subgroup pipe-b-wait-forked-hang:
pass -> INCOMPLETE (shard-apl)
Subgroup pipe-c-query-busy-hang:
pass -> INCOMPLETE (shard-apl)
Subgroup pipe-c-ts-continuation-idle-hang:
pass -> INCOMPLETE (shard-apl)
Subgroup pipe-c-wait-forked-hang:
pass -> INCOMPLETE (shard-apl)
Test perf:
Subgroup gen8-unprivileged-single-ctx-counters:
pass -> FAIL (shard-apl)
---- Known issues:
Test drv_missed_irq:
pass -> SKIP (shard-apl) fdo#103199
Test gem_eio:
Subgroup hibernate:
pass -> INCOMPLETE (shard-apl) fdo#103927
Subgroup in-flight-suspend:
pass -> INCOMPLETE (shard-apl) fdo#103375
Test kms_cursor_crc:
Subgroup cursor-128x128-suspend:
incomplete -> PASS (shard-hsw) fdo#103540
Test kms_flip:
Subgroup 2x-plain-flip-ts-check:
pass -> FAIL (shard-hsw) fdo#100368
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-apl) fdo#99912
fdo#103199 https://bugs.freedesktop.org/show_bug.cgi?id=103199
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
shard-apl total:2211 pass:1134 dwarn:1 dfail:1 fail:3 skip:1049 time:4742s
shard-hsw total:3484 pass:1773 dwarn:1 dfail:0 fail:2 skip:1707 time:11748s
shard-snb total:3484 pass:1363 dwarn:1 dfail:0 fail:3 skip:2117 time:7028s
Blacklisted hosts:
shard-kbl total:2038 pass:1110 dwarn:1 dfail:1 fail:8 skip:892 time:2827s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8477/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v4 1/7] drm/i915: Correctly handle error path in i915_gem_init_hw
2018-03-23 15:14 [PATCH v4 1/7] drm/i915: Correctly handle error path in i915_gem_init_hw Michal Wajdeczko
` (7 preceding siblings ...)
2018-03-23 20:15 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2018-03-26 10:16 ` Sagar Arun Kamble
8 siblings, 0 replies; 14+ messages in thread
From: Sagar Arun Kamble @ 2018-03-26 10:16 UTC (permalink / raw)
To: Michal Wajdeczko, intel-gfx
On 3/23/2018 8:44 PM, Michal Wajdeczko wrote:
> In function gem_init_hw() we are calling uc_init_hw() but in case
> of error later in function, we missed to call matching uc_fini_hw()
>
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
Looks good.
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 802df8e..7fad180 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -5171,9 +5171,15 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
>
> /* Only when the HW is re-initialised, can we replay the requests */
> ret = __i915_gem_restart_engines(dev_priv);
> + if (ret)
> + goto cleanup_uc;
> out:
> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> return ret;
> +
> +cleanup_uc:
> + intel_uc_fini_hw(dev_priv);
> + goto out;
> }
>
> static int __intel_engines_record_defaults(struct drm_i915_private *i915)
--
Thanks,
Sagar
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v4 2/7] drm/i915/uc: Disable GuC submission during sanitize
2018-03-23 15:14 ` [PATCH v4 2/7] drm/i915/uc: Disable GuC submission during sanitize Michal Wajdeczko
@ 2018-03-26 10:36 ` Sagar Arun Kamble
2018-03-27 16:58 ` Michal Wajdeczko
0 siblings, 1 reply; 14+ messages in thread
From: Sagar Arun Kamble @ 2018-03-26 10:36 UTC (permalink / raw)
To: Michal Wajdeczko, intel-gfx
On 3/23/2018 8:44 PM, Michal Wajdeczko wrote:
> We should not leave GuC submission enabled after sanitize,
> as we are going to reset all GuC/HuC hardware.
>
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
Either we need now destroy the doorbells cleanly or remove the below
comment from clients_doorbell_fini:
/*
* By the time we're here, GuC has already been reset.
* Instead of trying (in vain) to communicate with it, let's just
* cleanup the doorbell HW and our internal state.
*/
One additional thing I feel we should do now is remove uc_suspend|resume
from gem_suspend|resume
because we don't want to do any GuC actions once we suspend it.
> ---
> drivers/gpu/drm/i915/intel_uc.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 34f8a2c..2389828 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -331,6 +331,9 @@ void intel_uc_sanitize(struct drm_i915_private *i915)
>
> GEM_BUG_ON(!HAS_GUC(i915));
>
> + if (USES_GUC_SUBMISSION(dev_priv))
> + intel_guc_submission_disable(guc);
> +
> guc_disable_communication(guc);
>
> intel_huc_sanitize(huc);
--
Thanks,
Sagar
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v4 3/7] drm/i915/uc: Fully sanitize uC in uc_fini_hw
2018-03-23 15:14 ` [PATCH v4 3/7] drm/i915/uc: Fully sanitize uC in uc_fini_hw Michal Wajdeczko
@ 2018-03-26 11:23 ` Sagar Arun Kamble
2018-03-27 17:07 ` Michal Wajdeczko
0 siblings, 1 reply; 14+ messages in thread
From: Sagar Arun Kamble @ 2018-03-26 11:23 UTC (permalink / raw)
To: Michal Wajdeczko, intel-gfx
On 3/23/2018 8:44 PM, Michal Wajdeczko wrote:
> Today uc_fini_hw is subset of uc_sanitize, but remaining
> code in sanitize function is also desired for uc_fini_hw.
> Instead of duplicating the code, just call uc_sanitize,
> but leave as separate function to maintain symmetry with
> uc_init_hw.
>
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
We should drop call to uc_fini_hw from gem_fini as part of this patch as
GuC won't be available then.
> ---
> drivers/gpu/drm/i915/intel_uc.c | 14 ++------------
> 1 file changed, 2 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 2389828..9ff0c5a 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -434,19 +434,9 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
> return ret;
> }
>
> -void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
> +void intel_uc_fini_hw(struct drm_i915_private *i915)
> {
> - struct intel_guc *guc = &dev_priv->guc;
> -
> - if (!USES_GUC(dev_priv))
> - return;
> -
> - GEM_BUG_ON(!HAS_GUC(dev_priv));
> -
> - if (USES_GUC_SUBMISSION(dev_priv))
> - intel_guc_submission_disable(guc);
> -
> - guc_disable_communication(guc);
> + intel_uc_sanitize(i915);
> }
>
> int intel_uc_suspend(struct drm_i915_private *i915)
--
Thanks,
Sagar
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v4 2/7] drm/i915/uc: Disable GuC submission during sanitize
2018-03-26 10:36 ` Sagar Arun Kamble
@ 2018-03-27 16:58 ` Michal Wajdeczko
0 siblings, 0 replies; 14+ messages in thread
From: Michal Wajdeczko @ 2018-03-27 16:58 UTC (permalink / raw)
To: intel-gfx, Sagar Arun Kamble
On Mon, 26 Mar 2018 12:36:05 +0200, Sagar Arun Kamble
<sagar.a.kamble@intel.com> wrote:
>
>
> On 3/23/2018 8:44 PM, Michal Wajdeczko wrote:
>> We should not leave GuC submission enabled after sanitize,
>> as we are going to reset all GuC/HuC hardware.
>>
>> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Either we need now destroy the doorbells cleanly or remove the below
> comment from clients_doorbell_fini:
> /*
> * By the time we're here, GuC has already been reset.
> * Instead of trying (in vain) to communicate with it, let's
> just
> * cleanup the doorbell HW and our internal state.
> */
Good catch!
I'll restore symmetric doorbell cleanup in separate patch right after this
one.
>
> One additional thing I feel we should do now is remove uc_suspend|resume
> from gem_suspend|resume
> because we don't want to do any GuC actions once we suspend it.
Hmm, I would keep it to maintain symmetry with gem, and in us_resume we
already have guard for checking unloaded/sanitized GuC.
/m
>> ---
>> drivers/gpu/drm/i915/intel_uc.c | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_uc.c
>> b/drivers/gpu/drm/i915/intel_uc.c
>> index 34f8a2c..2389828 100644
>> --- a/drivers/gpu/drm/i915/intel_uc.c
>> +++ b/drivers/gpu/drm/i915/intel_uc.c
>> @@ -331,6 +331,9 @@ void intel_uc_sanitize(struct drm_i915_private
>> *i915)
>> GEM_BUG_ON(!HAS_GUC(i915));
>> + if (USES_GUC_SUBMISSION(dev_priv))
>> + intel_guc_submission_disable(guc);
>> +
>> guc_disable_communication(guc);
>> intel_huc_sanitize(huc);
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v4 3/7] drm/i915/uc: Fully sanitize uC in uc_fini_hw
2018-03-26 11:23 ` Sagar Arun Kamble
@ 2018-03-27 17:07 ` Michal Wajdeczko
0 siblings, 0 replies; 14+ messages in thread
From: Michal Wajdeczko @ 2018-03-27 17:07 UTC (permalink / raw)
To: intel-gfx, Sagar Arun Kamble
On Mon, 26 Mar 2018 13:23:21 +0200, Sagar Arun Kamble
<sagar.a.kamble@intel.com> wrote:
>
>
> On 3/23/2018 8:44 PM, Michal Wajdeczko wrote:
>> Today uc_fini_hw is subset of uc_sanitize, but remaining
>> code in sanitize function is also desired for uc_fini_hw.
>> Instead of duplicating the code, just call uc_sanitize,
>> but leave as separate function to maintain symmetry with
>> uc_init_hw.
>>
>> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> We should drop call to uc_fini_hw from gem_fini as part of this patch as
> GuC won't be available then.
But we will need it in gem_fini to properly finish our cleanup on unload.
Maybe to keep symmetry, we should add i915_gem_fini_hw and call it from
there ? See cleanup inside i915_gem_init_hw.
/m
>> ---
>> drivers/gpu/drm/i915/intel_uc.c | 14 ++------------
>> 1 file changed, 2 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_uc.c
>> b/drivers/gpu/drm/i915/intel_uc.c
>> index 2389828..9ff0c5a 100644
>> --- a/drivers/gpu/drm/i915/intel_uc.c
>> +++ b/drivers/gpu/drm/i915/intel_uc.c
>> @@ -434,19 +434,9 @@ int intel_uc_init_hw(struct drm_i915_private
>> *dev_priv)
>> return ret;
>> }
>> -void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
>> +void intel_uc_fini_hw(struct drm_i915_private *i915)
>> {
>> - struct intel_guc *guc = &dev_priv->guc;
>> -
>> - if (!USES_GUC(dev_priv))
>> - return;
>> -
>> - GEM_BUG_ON(!HAS_GUC(dev_priv));
>> -
>> - if (USES_GUC_SUBMISSION(dev_priv))
>> - intel_guc_submission_disable(guc);
>> -
>> - guc_disable_communication(guc);
>> + intel_uc_sanitize(i915);
>> }
>> int intel_uc_suspend(struct drm_i915_private *i915)
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^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2018-03-27 17:07 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-23 15:14 [PATCH v4 1/7] drm/i915: Correctly handle error path in i915_gem_init_hw Michal Wajdeczko
2018-03-23 15:14 ` [PATCH v4 2/7] drm/i915/uc: Disable GuC submission during sanitize Michal Wajdeczko
2018-03-26 10:36 ` Sagar Arun Kamble
2018-03-27 16:58 ` Michal Wajdeczko
2018-03-23 15:14 ` [PATCH v4 3/7] drm/i915/uc: Fully sanitize uC in uc_fini_hw Michal Wajdeczko
2018-03-26 11:23 ` Sagar Arun Kamble
2018-03-27 17:07 ` Michal Wajdeczko
2018-03-23 15:14 ` [PATCH v4 4/7] drm/i915/uc: Use correct error code for GuC initialization failure Michal Wajdeczko
2018-03-23 15:14 ` [PATCH v4 5/7] drm/i915/uc: Use helper functions to detect fw load status Michal Wajdeczko
2018-03-23 15:14 ` [PATCH v4 6/7] drm/i915/uc: Trivial s/dev_priv/i915 in intel_uc.c Michal Wajdeczko
2018-03-23 15:14 ` [PATCH v4 7/7] HAX: Enable GuC for CI Michal Wajdeczko
2018-03-23 17:18 ` ✓ Fi.CI.BAT: success for series starting with [v4,1/7] drm/i915: Correctly handle error path in i915_gem_init_hw Patchwork
2018-03-23 20:15 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-03-26 10:16 ` [PATCH v4 1/7] " Sagar Arun Kamble
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