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* [ovmf baseline-only test] 71645: tolerable FAIL
@ 2017-07-06  1:31 Platform Team regression test user
  0 siblings, 0 replies; only message in thread
From: Platform Team regression test user @ 2017-07-06  1:31 UTC (permalink / raw)
  To: xen-devel, osstest-admin

This run is configured for baseline tests only.

flight 71645 ovmf real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/71645/

Failures :-/ but no regressions.

Regressions which are regarded as allowable (not blocking):
 build-i386-libvirt            5 libvirt-build                fail   like 71632
 build-amd64-libvirt           5 libvirt-build                fail   like 71632

version targeted for testing:
 ovmf                 49be9c3c20cea7477b9c9e390c9f97735760e216
baseline version:
 ovmf                 1e6add9e476696461526163bde843570cfdffb39

Last test of basis    71632  2017-07-04 06:16:49 Z    1 days
Testing same since    71645  2017-07-05 07:18:33 Z    0 days    1 attempts

------------------------------------------------------------
People who touched revisions under test:
  Ruiyu Ni <ruiyu.ni@intel.com>

jobs:
 build-amd64-xsm                                              pass    
 build-i386-xsm                                               pass    
 build-amd64                                                  pass    
 build-i386                                                   pass    
 build-amd64-libvirt                                          fail    
 build-i386-libvirt                                           fail    
 build-amd64-pvops                                            pass    
 build-i386-pvops                                             pass    
 test-amd64-amd64-xl-qemuu-ovmf-amd64                         pass    
 test-amd64-i386-xl-qemuu-ovmf-amd64                          pass    


------------------------------------------------------------
sg-report-flight on osstest.xs.citrite.net
logs: /home/osstest/logs
images: /home/osstest/images

Logs, config files, etc. are available at
    http://osstest.xs.citrite.net/~osstest/testlogs/logs

Test harness code can be found at
    http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary


Push not applicable.

------------------------------------------------------------
commit 49be9c3c20cea7477b9c9e390c9f97735760e216
Author: Ruiyu Ni <ruiyu.ni@intel.com>
Date:   Mon Jul 3 17:53:49 2017 +0800

    MdeModulePkg/XhciDxe: Check timeout URB again after stopping endpoint
    
    This fixes BULK data loss when transfer is detected as timeout but
    finished just before stopping endpoint.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
    Reviewed-by: Hao Wu <hao.a.wu@intel.com>
    Cc: Star Zeng <star.zeng@intel.com>
    Cc: Feng Tian <feng.tian@intel.com>

commit 41fb8ce93930c33931a54550b12e1247fb86c805
Author: Ruiyu Ni <ruiyu.ni@intel.com>
Date:   Wed Jun 28 17:11:34 2017 +0800

    MdeModulePkg/XhciDxe: Separate common logic to XhcTransfer
    
    The patch separates the common logic in XhcControlTransfer,
    XhcBulkTransfer and XhcSyncIntTransfer to a sub-routine
    XhcTransfer. It doesn't have functionality impact.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
    Reviewed-by: Hao Wu <hao.a.wu@intel.com>
    Cc: Star Zeng <star.zeng@intel.com>
    Cc: Feng Tian <feng.tian@intel.com>

commit 396ae94d46906c52875054a0487d37cad2ff1216
Author: Ruiyu Ni <ruiyu.ni@intel.com>
Date:   Wed Jun 28 16:56:09 2017 +0800

    MdeModulePkg/XhciDxe: Dump the CMD/EVENT/INT/BULK ring information
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
    Reviewed-by: Hao Wu <hao.a.wu@intel.com>
    Cc: Star Zeng <star.zeng@intel.com>
    Cc: Feng Tian <feng.tian@intel.com>

commit 5a4b3388aaca684db837fadf404c98852e8449c8
Author: Ruiyu Ni <ruiyu.ni@intel.com>
Date:   Wed Jun 28 16:55:12 2017 +0800

    MdeModulePkg/XhciDxe: Refine IsTransferRingTrb and IsAsyncIntTrb
    
    Current implementation of IsTransferRingTrb only checks whether
    the TRB is in the RING of the URB.
    The patch enhanced the logic to check that whether the TRB belongs
    to the transaction of URB.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
    Reviewed-by: Hao Wu <hao.a.wu@intel.com>
    Cc: Star Zeng <star.zeng@intel.com>
    Cc: Feng Tian <feng.tian@intel.com>

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2017-07-06  1:31 [ovmf baseline-only test] 71645: tolerable FAIL Platform Team regression test user

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