From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x227kbOJ4+Af8jyzUUxfPp5PxKx7ojnlDozgrE3afrweiarFiqFjPHjctn3T3c0KnLZttZ1gM ARC-Seal: i=1; a=rsa-sha256; t=1516978996; cv=none; d=google.com; s=arc-20160816; b=Z7jD8azKoUl+qx9iHrr105WZswO7Hd7qLvEttMCeNAsvsTJmjMffbcslh7FWl75vNp SW0XZUFRgmJXy8PvfqqtNKZcTVKrBaU/7tnpx/5We8dSdL7ekfRtqG0jbIzoI8ByubKv 5eg6ROqJ0sBotlWzn1YUZaCsLSFVM4KGi7+ijmH7RLKM+fKeiG4DWXnLMxxtCwenZs7O /P0xVSIE7/dqTdIBTvwe535BjgzTSuVAuwyBFSUX9Vk9xJsIgYPZB2dwXDBZzeFqqQqB 7IpWvj0VrRy9qwESgKNlb4OEcJk516TsEiLcnRCf76jtorhTH5/pPzbsSFyZYEFZf339 b3ow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=precedence:content-disposition:content-transfer-encoding :mime-version:robot-unsubscribe:robot-id:git-commit-id:subject:to :references:in-reply-to:reply-to:cc:message-id:from:sender:date :arc-authentication-results; bh=MWEGBjNms5OOdGFOBP2HEdIetrQp0sJot8dMr7vuoYs=; b=yttDazcSAEfqscZLz8nhYkatoU2b8lqKSzWjAE6Tkm7XujiZ55+OB3toOdYBagaKyF 1HhiXwDNZclML+vush42ss/ar0bXJ73Efoc9flo1d8of0xI8BOVKQsNPjRrnFeU4HJia Sz4Dn2QYJNAEgHr2FJG3846bOAjAeZFVHowsADAFVA2VdvGCtmKF4aLZNy/tplWM+x6t 2qJ6nhL74mKDSbrYq/ta7ufmPZQGrTAt+rRsgLjG3Y63MyzOuh2D+EKwLjamxbuCo+d9 6UXp+4BRX3Y0rAjRcYC15B+3QaBN6s3xxnA9tyT+H2nl5Oc1impr5VhFkEjXunYGrhFg Vz6w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of tipbot@zytor.com designates 65.50.211.136 as permitted sender) smtp.mailfrom=tipbot@zytor.com Authentication-Results: mx.google.com; spf=pass (google.com: domain of tipbot@zytor.com designates 65.50.211.136 as permitted sender) smtp.mailfrom=tipbot@zytor.com Date: Fri, 26 Jan 2018 07:00:58 -0800 Sender: tip tree robot From: tip-bot for David Woodhouse Message-ID: Cc: dwmw@amazon.co.uk, linux-kernel@vger.kernel.org, gregkh@linuxfoundation.org, hpa@zytor.com, mingo@kernel.org, tglx@linutronix.de Reply-To: gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, dwmw@amazon.co.uk, tglx@linutronix.de, mingo@kernel.org, hpa@zytor.com In-Reply-To: <1516896855-7642-5-git-send-email-dwmw@amazon.co.uk> References: <1516896855-7642-5-git-send-email-dwmw@amazon.co.uk> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/pti] x86/msr: Add definitions for new speculation control MSRs Git-Commit-ID: 1e340c60d0dd3ae07b5bedc16a0469c14b9f3410 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590555835178069748?= X-GMAIL-MSGID: =?utf-8?q?1590667767961353427?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: Commit-ID: 1e340c60d0dd3ae07b5bedc16a0469c14b9f3410 Gitweb: https://git.kernel.org/tip/1e340c60d0dd3ae07b5bedc16a0469c14b9f3410 Author: David Woodhouse AuthorDate: Thu, 25 Jan 2018 16:14:12 +0000 Committer: Thomas Gleixner CommitDate: Fri, 26 Jan 2018 15:53:17 +0100 x86/msr: Add definitions for new speculation control MSRs Add MSR and bit definitions for SPEC_CTRL, PRED_CMD and ARCH_CAPABILITIES. See Intel's 336996-Speculative-Execution-Side-Channel-Mitigations.pdf Signed-off-by: David Woodhouse Signed-off-by: Thomas Gleixner Reviewed-by: Greg Kroah-Hartman Cc: gnomes@lxorguk.ukuu.org.uk Cc: ak@linux.intel.com Cc: ashok.raj@intel.com Cc: dave.hansen@intel.com Cc: karahmed@amazon.de Cc: arjan@linux.intel.com Cc: torvalds@linux-foundation.org Cc: peterz@infradead.org Cc: bp@alien8.de Cc: pbonzini@redhat.com Cc: tim.c.chen@linux.intel.com Cc: gregkh@linux-foundation.org Link: https://lkml.kernel.org/r/1516896855-7642-5-git-send-email-dwmw@amazon.co.uk --- arch/x86/include/asm/msr-index.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index fa11fb1..eb83ff1 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -39,6 +39,13 @@ /* Intel MSRs. Some also available on other CPUs */ +#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ +#define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted Speculation */ +#define SPEC_CTRL_STIBP (1 << 1) /* Single Thread Indirect Branch Predictors */ + +#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ +#define PRED_CMD_IBPB (1 << 0) /* Indirect Branch Prediction Barrier */ + #define MSR_PPIN_CTL 0x0000004e #define MSR_PPIN 0x0000004f @@ -57,6 +64,11 @@ #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) #define MSR_MTRRcap 0x000000fe + +#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a +#define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */ +#define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */ + #define MSR_IA32_BBL_CR_CTL 0x00000119 #define MSR_IA32_BBL_CR_CTL3 0x0000011e