From: tip-bot for Wan Zongshun <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: hpa@zytor.com, mingo@kernel.org, tony.luck@intel.com, bp@suse.de,
Vincent.Wan@amd.com, ray.huang@amd.com, dvlasenk@redhat.com,
bp@alien8.de, tglx@linutronix.de, aravind.gopalakrishnan@amd.com,
peterz@infradead.org, linux-kernel@vger.kernel.org,
torvalds@linux-foundation.org, luto@kernel.org
Subject: [tip:x86/cpu] x86/cpu: Add CLZERO detection
Date: Sun, 1 Nov 2015 02:28:30 -0800 [thread overview]
Message-ID: <tip-2167ceabf34163727ca4e283c0f030e3960932e5@git.kernel.org> (raw)
In-Reply-To: <1446207099-24948-4-git-send-email-bp@alien8.de>
Commit-ID: 2167ceabf34163727ca4e283c0f030e3960932e5
Gitweb: http://git.kernel.org/tip/2167ceabf34163727ca4e283c0f030e3960932e5
Author: Wan Zongshun <Vincent.Wan@amd.com>
AuthorDate: Fri, 30 Oct 2015 13:11:39 +0100
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Sun, 1 Nov 2015 11:26:23 +0100
x86/cpu: Add CLZERO detection
AMD Fam17h processors introduce support for the CLZERO
instruction. It zeroes out the 64 byte cache line specified in
RAX.
Add the bit here to allow /proc/cpuinfo to list the feature.
Boris: we're adding this as a separate ->x86_capability leaf
because CPUID_80000008_EBX is going to contain more feature bits
and it will fill out with time.
Signed-off-by: Wan Zongshun <Vincent.Wan@amd.com>
Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>
[ Wrap code in patch form, fix comments. ]
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Huang Rui <ray.huang@amd.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Link: http://lkml.kernel.org/r/1446207099-24948-4-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/include/asm/cpufeature.h | 5 ++++-
arch/x86/kernel/cpu/common.c | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 9727b3b..e4f8010 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -12,7 +12,7 @@
#include <asm/disabled-features.h>
#endif
-#define NCAPINTS 13 /* N 32-bit words worth of info */
+#define NCAPINTS 14 /* N 32-bit words worth of info */
#define NBUGINTS 1 /* N 32-bit bug flags */
/*
@@ -255,6 +255,9 @@
/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */
#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */
+/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */
+#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */
+
/*
* BUG word(s)
*/
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index de22ea7..4ddd780 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -670,6 +670,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
c->x86_virt_bits = (eax >> 8) & 0xff;
c->x86_phys_bits = eax & 0xff;
+ c->x86_capability[13] = cpuid_ebx(0x80000008);
}
#ifdef CONFIG_X86_32
else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
prev parent reply other threads:[~2015-11-01 10:29 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-30 12:11 [PATCH 0/3] tip-queue 2015-10-30 Borislav Petkov
2015-10-30 12:11 ` [PATCH 1/3] x86/mce: Add a Scalable MCA vendor flags bit Borislav Petkov
2015-11-01 10:27 ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan
2015-10-30 12:11 ` [PATCH 2/3] x86/mce: Add a default case to the switch in __mcheck_cpu_ancient_init() Borislav Petkov
2015-11-01 10:28 ` [tip:ras/core] " tip-bot for Borislav Petkov
2015-10-30 12:11 ` [PATCH 3/3] x86/cpu: Add CLZERO detection Borislav Petkov
2015-11-01 10:28 ` tip-bot for Wan Zongshun [this message]
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