From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755299AbcIELxU (ORCPT ); Mon, 5 Sep 2016 07:53:20 -0400 Received: from terminus.zytor.com ([198.137.202.10]:36248 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755229AbcIELxT (ORCPT ); Mon, 5 Sep 2016 07:53:19 -0400 Date: Mon, 5 Sep 2016 04:52:42 -0700 From: tip-bot for Stephane Eranian Message-ID: Cc: torvalds@linux-foundation.org, alexander.shishkin@linux.intel.com, peterz@infradead.org, vincent.weaver@maine.edu, eranian@google.com, kan.liang@intel.com, mingo@kernel.org, hpa@zytor.com, tglx@linutronix.de, jolsa@redhat.com, acme@redhat.com, linux-kernel@vger.kernel.org Reply-To: kan.liang@intel.com, eranian@google.com, vincent.weaver@maine.edu, torvalds@linux-foundation.org, alexander.shishkin@linux.intel.com, peterz@infradead.org, hpa@zytor.com, mingo@kernel.org, acme@redhat.com, jolsa@redhat.com, tglx@linutronix.de, linux-kernel@vger.kernel.org In-Reply-To: <1471378190-17276-2-git-send-email-kan.liang@intel.com> References: <1471378190-17276-2-git-send-email-kan.liang@intel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf/x86/intel/uncore: Handle non-standard counter offset Git-Commit-ID: 24cf84672e0a1e0d13f3894b60cd820a0140342a X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 24cf84672e0a1e0d13f3894b60cd820a0140342a Gitweb: http://git.kernel.org/tip/24cf84672e0a1e0d13f3894b60cd820a0140342a Author: Stephane Eranian AuthorDate: Tue, 16 Aug 2016 16:09:49 -0400 Committer: Ingo Molnar CommitDate: Mon, 5 Sep 2016 13:15:08 +0200 perf/x86/intel/uncore: Handle non-standard counter offset The offset of the counters for UPI and M2M boxes on Skylake server is non-standard (8 bytes apart). This patch introduces a custom flag UNCORE_BOX_FLAG_CTL_OFFS8 to specially handle it. Signed-off-by: Stephane Eranian Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: Vince Weaver Link: http://lkml.kernel.org/r/1471378190-17276-2-git-send-email-kan.liang@intel.com Signed-off-by: Ingo Molnar --- arch/x86/events/intel/uncore.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h index 78b9c23..a43175f 100644 --- a/arch/x86/events/intel/uncore.h +++ b/arch/x86/events/intel/uncore.h @@ -120,6 +120,7 @@ struct intel_uncore_box { }; #define UNCORE_BOX_FLAG_INITIATED 0 +#define UNCORE_BOX_FLAG_CTL_OFFS8 1 /* event config registers are 8-byte apart */ struct uncore_event_desc { struct kobj_attribute attr; @@ -172,6 +173,9 @@ static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box) static inline unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx) { + if (test_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags)) + return idx * 8 + box->pmu->type->event_ctl; + return idx * 4 + box->pmu->type->event_ctl; }