From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754005AbcBALlt (ORCPT ); Mon, 1 Feb 2016 06:41:49 -0500 Received: from terminus.zytor.com ([198.137.202.10]:57287 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753663AbcBALlr (ORCPT ); Mon, 1 Feb 2016 06:41:47 -0500 Date: Mon, 1 Feb 2016 03:40:52 -0800 From: tip-bot for Aravind Gopalakrishnan Message-ID: Cc: linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, mingo@kernel.org, bp@alien8.de, peterz@infradead.org, tglx@linutronix.de, torvalds@linux-foundation.org, Aravind.Gopalakrishnan@amd.com, bp@suse.de, tony.luck@intel.com, hpa@zytor.com, fengguang.wu@intel.com Reply-To: tglx@linutronix.de, peterz@infradead.org, bp@alien8.de, mingo@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, fengguang.wu@intel.com, hpa@zytor.com, tony.luck@intel.com, Aravind.Gopalakrishnan@amd.com, bp@suse.de, torvalds@linux-foundation.org In-Reply-To: <1453750913-4781-5-git-send-email-bp@alien8.de> References: <1453750913-4781-5-git-send-email-bp@alien8.de> To: linux-tip-commits@vger.kernel.org Subject: [tip:ras/core] x86/mce/AMD: Do not perform shared bank check for future processors Git-Commit-ID: 284b965c146f482b4a411133f62288d52b7e3a72 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 284b965c146f482b4a411133f62288d52b7e3a72 Gitweb: http://git.kernel.org/tip/284b965c146f482b4a411133f62288d52b7e3a72 Author: Aravind Gopalakrishnan AuthorDate: Mon, 25 Jan 2016 20:41:49 +0100 Committer: Ingo Molnar CommitDate: Mon, 1 Feb 2016 10:53:56 +0100 x86/mce/AMD: Do not perform shared bank check for future processors Fam17h and above should not require a check to see if a bank is shared or not. For shared banks, there will always be only one core that has visibility over the MSRs and only that particular core will be allowed to write to the MSRs. Fix the code to return early if we have Scalable MCA support. No change in functionality for earlier processors. Signed-off-by: Aravind Gopalakrishnan Signed-off-by: Fengguang Wu [ Massaged the changelog text, fixed kbuild test robot build warning. ] Signed-off-by: Borislav Petkov Cc: Borislav Petkov Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: Tony Luck Cc: linux-edac Link: http://lkml.kernel.org/r/1453750913-4781-5-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar --- arch/x86/kernel/cpu/mcheck/mce_amd.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index e99b150..3068ce2 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -84,6 +84,13 @@ struct thresh_restart { static inline bool is_shared_bank(int bank) { + /* + * Scalable MCA provides for only one core to have access to the MSRs of + * a shared bank. + */ + if (mce_flags.smca) + return false; + /* Bank 4 is for northbridge reporting and is thus shared */ return (bank == 4); }