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From: tip-bot for Borislav Petkov <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: bp@alien8.de, hpa@zytor.com, tony.luck@intel.com,
	linux-kernel@vger.kernel.org, torvalds@linux-foundation.org,
	mingo@kernel.org, Aravind.Gopalakrishnan@amd.com,
	peterz@infradead.org, bp@suse.de, tglx@linutronix.de
Subject: [tip:ras/core] x86/mce/AMD: Carve out threshold block preparation
Date: Mon, 1 Feb 2016 03:41:55 -0800	[thread overview]
Message-ID: <tip-429893b16d35d309ed6b35136aad5f908a08d9b9@git.kernel.org> (raw)
In-Reply-To: <1453750913-4781-8-git-send-email-bp@alien8.de>

Commit-ID:  429893b16d35d309ed6b35136aad5f908a08d9b9
Gitweb:     http://git.kernel.org/tip/429893b16d35d309ed6b35136aad5f908a08d9b9
Author:     Borislav Petkov <bp@suse.de>
AuthorDate: Mon, 25 Jan 2016 20:41:52 +0100
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Mon, 1 Feb 2016 10:53:58 +0100

x86/mce/AMD: Carve out threshold block preparation

mce_amd_feature_init() was getting pretty fat, carve out the
threshold_block setup into a separate function in order to
simplify flow and make it more understandable.

No functionality change.

Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Link: http://lkml.kernel.org/r/1453750913-4781-8-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 87 ++++++++++++++++++++----------------
 1 file changed, 49 insertions(+), 38 deletions(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index a77a452..f2860a1 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -267,14 +267,59 @@ static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
 	wrmsr(MSR_CU_DEF_ERR, low, high);
 }
 
+static int
+prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
+			int offset, u32 misc_high)
+{
+	unsigned int cpu = smp_processor_id();
+	struct threshold_block b;
+	int new;
+
+	if (!block)
+		per_cpu(bank_map, cpu) |= (1 << bank);
+
+	memset(&b, 0, sizeof(b));
+	b.cpu			= cpu;
+	b.bank			= bank;
+	b.block			= block;
+	b.address		= addr;
+	b.interrupt_capable	= lvt_interrupt_supported(bank, misc_high);
+
+	if (!b.interrupt_capable)
+		goto done;
+
+	b.interrupt_enable = 1;
+
+	if (mce_flags.smca) {
+		u32 smca_low, smca_high;
+
+		/* Gather LVT offset for thresholding: */
+		if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
+			goto out;
+
+		new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
+	} else {
+		new = (misc_high & MASK_LVTOFF_HI) >> 20;
+	}
+
+	offset = setup_APIC_mce_threshold(offset, new);
+
+	if ((offset == new) && (mce_threshold_vector != amd_threshold_interrupt))
+		mce_threshold_vector = amd_threshold_interrupt;
+
+done:
+	mce_threshold_block_init(&b, offset);
+
+out:
+	return offset;
+}
+
 /* cpu init entry point, called from mce.c with preempt off */
 void mce_amd_feature_init(struct cpuinfo_x86 *c)
 {
-	struct threshold_block b;
-	unsigned int cpu = smp_processor_id();
 	u32 low = 0, high = 0, address = 0;
 	unsigned int bank, block;
-	int offset = -1, new;
+	int offset = -1;
 
 	for (bank = 0; bank < mca_cfg.banks; ++bank) {
 		for (block = 0; block < NR_BLOCKS; ++block) {
@@ -299,41 +344,7 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
 			     (high & MASK_LOCKED_HI))
 				continue;
 
-			if (!block)
-				per_cpu(bank_map, cpu) |= (1 << bank);
-
-			memset(&b, 0, sizeof(b));
-			b.cpu			= cpu;
-			b.bank			= bank;
-			b.block			= block;
-			b.address		= address;
-			b.interrupt_capable	= lvt_interrupt_supported(bank, high);
-
-			if (!b.interrupt_capable)
-				goto init;
-
-			b.interrupt_enable = 1;
-
-			if (mce_flags.smca) {
-				u32 smca_low, smca_high;
-
-				/* Gather LVT offset for thresholding: */
-				if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
-					break;
-
-				new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
-			} else {
-				new = (high & MASK_LVTOFF_HI) >> 20;
-			}
-
-			offset  = setup_APIC_mce_threshold(offset, new);
-
-			if ((offset == new) &&
-			    (mce_threshold_vector != amd_threshold_interrupt))
-				mce_threshold_vector = amd_threshold_interrupt;
-
-init:
-			mce_threshold_block_init(&b, offset);
+			offset = prepare_threshold_block(bank, block, address, offset, high);
 		}
 	}
 

  reply	other threads:[~2016-02-01 11:42 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-01-25 19:41 [PATCH 0/8] tip-queue 2016-01-25 Borislav Petkov
2016-01-25 19:41 ` [PATCH 1/8] x86/traps.c: Refactor preemption and interrupt flag handling Borislav Petkov
2016-02-01 11:39   ` [tip:x86/asm] x86/entry/traps: " tip-bot for Alexander Kuleshov
2016-01-25 19:41 ` [PATCH 2/8] x86/cpufeature: Use enum cpuid_leafs instead of magic numbers Borislav Petkov
2016-02-01 11:40   ` [tip:x86/cpu] " tip-bot for Huaitong Han
2016-01-25 19:41 ` [PATCH 3/8] x86/mce: Fix order of AMD MCE init function call Borislav Petkov
2016-02-01 11:40   ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan
2016-01-25 19:41 ` [PATCH 4/8] x86/mce/AMD: Do not perform shared bank check for future processors Borislav Petkov
2016-02-01 11:40   ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan
2016-01-25 19:41 ` [PATCH 5/8] x86/mce/AMD: Reduce number of blocks scanned per bank Borislav Petkov
2016-02-01 11:41   ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan
2016-01-25 19:41 ` [PATCH 6/8] x86/mce/AMD: Fix LVT offset configuration for thresholding Borislav Petkov
2016-02-01 11:41   ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan
2016-01-25 19:41 ` [PATCH 7/8] x86/mce/AMD: Carve out threshold block preparation Borislav Petkov
2016-02-01 11:41   ` tip-bot for Borislav Petkov [this message]
2016-01-25 19:41 ` [PATCH 8/8] x86/mce/AMD: Set MCAX Enable bit Borislav Petkov
2016-02-01 11:42   ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan

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