From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753541AbbHVJV6 (ORCPT ); Sat, 22 Aug 2015 05:21:58 -0400 Received: from terminus.zytor.com ([198.137.202.10]:33813 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753320AbbHVJVz (ORCPT ); Sat, 22 Aug 2015 05:21:55 -0400 Date: Sat, 22 Aug 2015 02:21:34 -0700 From: tip-bot for Tim Chen Message-ID: Cc: herbert@gondor.apana.org.au, bp@suse.de, dave.hansen@intel.com, mingo@kernel.org, tglx@linutronix.de, mouli_7982@yahoo.com, tim.c.chen@linux.intel.com, linux-kernel@vger.kernel.org, hpa@zytor.com Reply-To: linux-kernel@vger.kernel.org, hpa@zytor.com, tim.c.chen@linux.intel.com, dave.hansen@intel.com, mingo@kernel.org, mouli_7982@yahoo.com, tglx@linutronix.de, herbert@gondor.apana.org.au, bp@suse.de In-Reply-To: <1440194206.3940.6.camel@schen9-mobl2> References: <1440194206.3940.6.camel@schen9-mobl2> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/cpufeature] x86/cpufeatures: Enable cpuid for Intel SHA extensions Git-Commit-ID: 488ca7d72d974e3c00ae73ed9f947590680bdf00 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 488ca7d72d974e3c00ae73ed9f947590680bdf00 Gitweb: http://git.kernel.org/tip/488ca7d72d974e3c00ae73ed9f947590680bdf00 Author: Tim Chen AuthorDate: Fri, 21 Aug 2015 14:56:46 -0700 Committer: Thomas Gleixner CommitDate: Sat, 22 Aug 2015 11:17:31 +0200 x86/cpufeatures: Enable cpuid for Intel SHA extensions Add Intel CPUID for Intel Secure Hash Algorithm Extensions. This feature provides new instructions for accelerated computation of SHA-1 and SHA-256. This allows the feature to be shown in the /proc/cpuinfo for cpus that support it. Refer to SHA extension programming guide in chapter 8.2 of the Intel Architecture Instruction Set Extensions Programming reference for definition of this feature's cpuid: CPUID.(EAX=07H, ECX=0):EBX.SHA [bit 29] = 1 https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf Originally-by: Chandramouli Narayanan Signed-off-by: Tim Chen Cc: Borislav Petkov Cc: Dave Hansen Cc: Herbert Xu Link: http://lkml.kernel.org/r/1440194206.3940.6.camel@schen9-mobl2 Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/cpufeature.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 3d6606f..a94f83d 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -239,6 +239,7 @@ #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */