From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751331AbeACQZi (ORCPT + 1 other); Wed, 3 Jan 2018 11:25:38 -0500 Received: from terminus.zytor.com ([65.50.211.136]:58513 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750968AbeACQZg (ORCPT ); Wed, 3 Jan 2018 11:25:36 -0500 Date: Wed, 3 Jan 2018 08:22:14 -0800 From: tip-bot for Thomas Gleixner Message-ID: Cc: mingo@kernel.org, bp@alien8.de, hpa@zytor.com, linux-kernel@vger.kernel.org, mroos@linux.ee, tglx@linutronix.de, thomas.lendacky@amd.com Reply-To: bp@alien8.de, mingo@kernel.org, linux-kernel@vger.kernel.org, mroos@linux.ee, hpa@zytor.com, tglx@linutronix.de, thomas.lendacky@amd.com In-Reply-To: References: To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/pti] x86/pti: Make sure the user/kernel PTEs match Git-Commit-ID: 52994c256df36fda9a715697431cba9daecb6b11 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: Commit-ID: 52994c256df36fda9a715697431cba9daecb6b11 Gitweb: https://git.kernel.org/tip/52994c256df36fda9a715697431cba9daecb6b11 Author: Thomas Gleixner AuthorDate: Wed, 3 Jan 2018 15:57:59 +0100 Committer: Thomas Gleixner CommitDate: Wed, 3 Jan 2018 15:57:59 +0100 x86/pti: Make sure the user/kernel PTEs match Meelis reported that his K8 Athlon64 emits MCE warnings when PTI is enabled: [Hardware Error]: Error Addr: 0x0000ffff81e000e0 [Hardware Error]: MC1 Error: L1 TLB multimatch. [Hardware Error]: cache level: L1, tx: INSN The address is in the entry area, which is mapped into kernel _AND_ user space. That's special because we switch CR3 while we are executing there. User mapping: 0xffffffff81e00000-0xffffffff82000000 2M ro PSE GLB x pmd Kernel mapping: 0xffffffff81000000-0xffffffff82000000 16M ro PSE x pmd So the K8 is complaining that the TLB entries differ. They differ in the GLB bit. Drop the GLB bit when installing the user shared mapping. Fixes: 6dc72c3cbca0 ("x86/mm/pti: Share entry text PMD") Reported-by: Meelis Roos Signed-off-by: Thomas Gleixner Tested-by: Meelis Roos Cc: Borislav Petkov Cc: Tom Lendacky Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/alpine.DEB.2.20.1801031407180.1957@nanos --- arch/x86/mm/pti.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/mm/pti.c b/arch/x86/mm/pti.c index bce8aea..2da28ba 100644 --- a/arch/x86/mm/pti.c +++ b/arch/x86/mm/pti.c @@ -367,7 +367,8 @@ static void __init pti_setup_espfix64(void) static void __init pti_clone_entry_text(void) { pti_clone_pmds((unsigned long) __entry_text_start, - (unsigned long) __irqentry_text_end, _PAGE_RW); + (unsigned long) __irqentry_text_end, + _PAGE_RW | _PAGE_GLOBAL); } /*