From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x225htSDsREImFAsGNxq8eu5auJiAv8hrUwAuDXQA8fBhkFK2Vc6E2n7+Ns5Mxu6nz3at0MOa ARC-Seal: i=1; a=rsa-sha256; t=1516978965; cv=none; d=google.com; s=arc-20160816; b=Rzc8V/uOnEcJY5x7DBvRvppxpsAh/LwF6inGel3OYJPY4RElOF1UqUHOk9h2VysW7f OKRPqb7DR+x+5U+s7bTvaQdwY1G8tec+U1m8h/i/+shzgColUfStCLRnugU+f1UirxcP tchLETmE8xUtU9Rb1Ra6yht5nKjhona2IE+YJ/YEK/cPfN8w+84Yb/MtZkhevqqEsGTQ RIMjOvy9pMI74fV+01hRWFP49KZiTZ5svc6RSIwAIVKpjJXTXgnMsJh2M+Gm2MoBOvMs JTxsMZ1mF6JQkTRPMgGtJEZprDkwjOh64yKDESPUNTpOzvMjEZ8mpH1r9a46VigSXF+O Bm8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=precedence:content-disposition:content-transfer-encoding :mime-version:robot-unsubscribe:robot-id:git-commit-id:subject:to :references:in-reply-to:reply-to:cc:message-id:from:sender:date :arc-authentication-results; bh=1Ero7tqeZ8duFmCqceEtowzJuQ6t5Awr1KL7gaRjZ0s=; b=dXTubRAOHOJEFFLGq17VBTKFYrTIESfGy51NbNsLGVsq5/qKZffj4zak3zYXfmI59z KRVOIBs1ufKA8tSxalx0y7GGKkltnFp8WN6d8wk04eUWUirQcwpywb+oJlXzWmQdJS3Z WVCHHehhyHflzm8f+uRhW3ml4mubnD7Js7Qp7/Tnwnv8WOfmX0BqvX+X/6dR/yYzhSdR dZsC8lptJy/bo8wrC6Eik9dP22X6sABxWX2T4/IIAQiLTr0hEyA1v+r5p8tkUyMS/51T JnjPP0uJmpDTq1FPFyULH+DyIz1IUXGYeOX9kmYAvFVUKnTnD++GwgB3nNYsYTH+XXwG xGng== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of tipbot@zytor.com designates 65.50.211.136 as permitted sender) smtp.mailfrom=tipbot@zytor.com Authentication-Results: mx.google.com; spf=pass (google.com: domain of tipbot@zytor.com designates 65.50.211.136 as permitted sender) smtp.mailfrom=tipbot@zytor.com Date: Fri, 26 Jan 2018 07:00:30 -0800 Sender: tip tree robot From: tip-bot for David Woodhouse Message-ID: Cc: hpa@zytor.com, gregkh@linuxfoundation.org, tglx@linutronix.de, dwmw@amazon.co.uk, thomas.lendacky@amd.com, linux-kernel@vger.kernel.org, mingo@kernel.org Reply-To: linux-kernel@vger.kernel.org, thomas.lendacky@amd.com, mingo@kernel.org, dwmw@amazon.co.uk, gregkh@linuxfoundation.org, tglx@linutronix.de, hpa@zytor.com In-Reply-To: <1516896855-7642-4-git-send-email-dwmw@amazon.co.uk> References: <1516896855-7642-4-git-send-email-dwmw@amazon.co.uk> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/pti] x86/cpufeatures: Add AMD feature bits for Speculation Control Git-Commit-ID: 5d10cbc91d9eb5537998b65608441b592eec65e7 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590555819438908618?= X-GMAIL-MSGID: =?utf-8?q?1590667736131292926?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: Commit-ID: 5d10cbc91d9eb5537998b65608441b592eec65e7 Gitweb: https://git.kernel.org/tip/5d10cbc91d9eb5537998b65608441b592eec65e7 Author: David Woodhouse AuthorDate: Thu, 25 Jan 2018 16:14:11 +0000 Committer: Thomas Gleixner CommitDate: Fri, 26 Jan 2018 15:53:17 +0100 x86/cpufeatures: Add AMD feature bits for Speculation Control AMD exposes the PRED_CMD/SPEC_CTRL MSRs slightly differently to Intel. See http://lkml.kernel.org/r/2b3e25cc-286d-8bd0-aeaf-9ac4aae39de8@amd.com Signed-off-by: David Woodhouse Signed-off-by: Thomas Gleixner Reviewed-by: Greg Kroah-Hartman Cc: Tom Lendacky Cc: gnomes@lxorguk.ukuu.org.uk Cc: ak@linux.intel.com Cc: ashok.raj@intel.com Cc: dave.hansen@intel.com Cc: karahmed@amazon.de Cc: arjan@linux.intel.com Cc: torvalds@linux-foundation.org Cc: peterz@infradead.org Cc: bp@alien8.de Cc: pbonzini@redhat.com Cc: tim.c.chen@linux.intel.com Cc: gregkh@linux-foundation.org Link: https://lkml.kernel.org/r/1516896855-7642-4-git-send-email-dwmw@amazon.co.uk --- arch/x86/include/asm/cpufeatures.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 0a51070..ae3212f 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -269,6 +269,9 @@ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ +#define X86_FEATURE_AMD_PRED_CMD (13*32+12) /* Prediction Command MSR (AMD) */ +#define X86_FEATURE_AMD_SPEC_CTRL (13*32+14) /* Speculation Control MSR only (AMD) */ +#define X86_FEATURE_AMD_STIBP (13*32+15) /* Single Thread Indirect Branch Predictors (AMD) */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */